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[PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property forma
From: |
Alistair Francis |
Subject: |
[PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC |
Date: |
Wed, 10 Jan 2024 18:56:53 +1000 |
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
The interrupts-extended property of PLIC only has 2 * hart number
fields when KVM enabled, copy 4 * hart number fields to fdt will
expose some uninitialized value.
In this patch, I also refactor the code about the setting of
interrupts-extended property of PLIC for improved readability.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231218090543.22353-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 47 +++++++++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a7c4c3508e..4194ddcef1 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -437,24 +437,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
"sifive,plic-1.0.0", "riscv,plic0"
};
- if (kvm_enabled()) {
- plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
- } else {
- plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
- }
-
- for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
- if (kvm_enabled()) {
- plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
- plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
- } else {
- plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
- plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
- plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
- plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
- }
- }
-
plic_phandles[socket] = (*phandle)++;
plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
@@ -467,8 +449,33 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
(char **)&plic_compat,
ARRAY_SIZE(plic_compat));
qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
- plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+
+ if (kvm_enabled()) {
+ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+ }
+
+ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
+ plic_cells,
+ s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ } else {
+ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
+ plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
+ plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+ }
+
+ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
+ plic_cells,
+ s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+ }
+
qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
--
2.43.0
- [PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT, (continued)
- [PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT, Alistair Francis, 2024/01/10
- [PULL 15/65] hw/riscv: virt: Make few IMSIC macros and functions public, Alistair Francis, 2024/01/10
- [PULL 16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC, Alistair Francis, 2024/01/10
- [PULL 17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT, Alistair Francis, 2024/01/10
- [PULL 20/65] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT, Alistair Francis, 2024/01/10
- [PULL 19/65] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT, Alistair Francis, 2024/01/10
- [PULL 21/65] hw/pci-host/gpex: Define properties for MMIO ranges, Alistair Francis, 2024/01/10
- [PULL 22/65] hw/riscv/virt: Update GPEX MMIO related properties, Alistair Francis, 2024/01/10
- [PULL 23/65] hw/riscv/virt-acpi-build.c: Add IO controllers and devices, Alistair Francis, 2024/01/10
- [PULL 24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT, Alistair Francis, 2024/01/10
- [PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC,
Alistair Francis <=
- [PULL 26/65] target/riscv: Add support for Zacas extension, Alistair Francis, 2024/01/10
- [PULL 18/65] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT, Alistair Francis, 2024/01/10
- [PULL 27/65] disas/riscv: Add amocas.[w,d,q] instructions, Alistair Francis, 2024/01/10
- [PULL 28/65] docs/system/riscv: document acpi parameter of virt machine, Alistair Francis, 2024/01/10
- [PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks, Alistair Francis, 2024/01/10
- [PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions, Alistair Francis, 2024/01/10
- [PULL 32/65] target/riscv: add rv64i CPU, Alistair Francis, 2024/01/10
- [PULL 40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Alistair Francis, 2024/01/10
- [PULL 41/65] target/riscv/tcg: handle profile MISA bits, Alistair Francis, 2024/01/10
- [PULL 33/65] target/riscv: add zicbop extension flag, Alistair Francis, 2024/01/10