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Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate curre
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From: |
Deepak Gupta |
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Subject: |
Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking |
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Date: |
Thu, 4 Jan 2024 16:46:29 -0800 |
On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
> +
> +bool riscv_cpu_bare_mode(CPURISCVState *env)
> +{
> + int satp_mode = 0;
> +#ifndef CONFIG_USER_ONLY
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> + satp_mode = get_field(env->satp, SATP32_MODE);
> + } else {
> + satp_mode = get_field(env->satp, SATP64_MODE);
> + }
> +#endif
> + return (satp_mode == VM_1_10_MBARE);
> +}
> +
Assume the CPU was in S or U with satp = non-bare mode but then a
transfer to M-mode happened.
In that case, even though the CPU is in M mode, the above function
will return non-bare mode and enforce
signed extension on M mode pointer masking (if enabled).
right or am I missing something here?
- [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8, Alexey Baturo, 2024/01/03
- [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code., Alexey Baturo, 2024/01/03
- [PATCH v3 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8, Alexey Baturo, 2024/01/03
- [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alexey Baturo, 2024/01/03
- Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking,
Deepak Gupta <=
- [PATCH v3 4/6] target/riscv: Add pointer masking tb flags, Alexey Baturo, 2024/01/03
- [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alexey Baturo, 2024/01/03
- [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking, Alexey Baturo, 2024/01/03