[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 1/6] linux-user/riscv: Add Zicboz block size to hwprobe
From: |
Alistair Francis |
Subject: |
[PULL 1/6] linux-user/riscv: Add Zicboz block size to hwprobe |
Date: |
Wed, 22 Nov 2023 15:37:55 +1000 |
From: Palmer Dabbelt <palmer@rivosinc.com>
Support for probing the Zicboz block size landed in Linux 6.6, which was
released a few weeks ago. This provides the user-configured block size
when Zicboz is enabled.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231110173716.24423-1-palmer@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
linux-user/syscall.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 16ca5ea7b6..e384e14248 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8808,6 +8808,8 @@ static int do_getdents64(abi_long dirfd, abi_long arg2,
abi_long count)
#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
+#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
+
struct riscv_hwprobe {
abi_llong key;
abi_ullong value;
@@ -8860,6 +8862,10 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
case RISCV_HWPROBE_KEY_CPUPERF_0:
__put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value);
break;
+ case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
+ value = cfg->ext_zicboz ? cfg->cboz_blocksize : 0;
+ __put_user(value, &pair->value);
+ break;
default:
__put_user(-1, &pair->key);
break;
--
2.42.0
- [PULL 0/6] riscv-to-apply queue, Alistair Francis, 2023/11/22
- [PULL 1/6] linux-user/riscv: Add Zicboz block size to hwprobe,
Alistair Francis <=
- [PULL 2/6] hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt(), Alistair Francis, 2023/11/22
- [PULL 3/6] target/riscv: don't verify ISA compatibility for zicntr and zihpm, Alistair Francis, 2023/11/22
- [PULL 4/6] riscv: Fix SiFive E CLINT clock frequency, Alistair Francis, 2023/11/22
- [PULL 5/6] target/riscv/cpu_helper.c: Invalid exception on MMU translation stage, Alistair Francis, 2023/11/22
- [PULL 6/6] target/riscv/cpu_helper.c: Fix mxr bit behavior, Alistair Francis, 2023/11/22
- Re: [PULL 0/6] riscv-to-apply queue, Stefan Hajnoczi, 2023/11/22
- Re: [PULL 0/6] riscv-to-apply queue, Michael Tokarev, 2023/11/25