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[PULL 31/49] target/riscv: Add cfg property for Zvkb extension
From: |
Alistair Francis |
Subject: |
[PULL 31/49] target/riscv: Add cfg property for Zvkb extension |
Date: |
Tue, 7 Nov 2023 12:29:27 +1000 |
From: Max Chou <max.chou@sifive.com>
After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is
defined as a proper subset of the Zvbb extension. And both the Zvkn and
Zvks shorthand extensions replace the included Zvbb extension by Zvkb
extnesion.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-4-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 1f0dac5c8a..c4b2fec024 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -90,6 +90,7 @@ struct RISCVCPUConfig {
bool ext_zve64d;
bool ext_zvbb;
bool ext_zvbc;
+ bool ext_zvkb;
bool ext_zvkg;
bool ext_zvkned;
bool ext_zvknha;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 87baae56a1..ad7a183a74 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -508,9 +508,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error
**errp)
* In principle Zve*x would also suffice here, were they supported
* in qemu
*/
- if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
- cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
- !cpu->cfg.ext_zve32f) {
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
+ cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
error_setg(errp,
"Vector crypto extensions require V or Zve* extensions");
return;
--
2.41.0
- [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01, (continued)
- [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01, Alistair Francis, 2023/11/06
- [PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 22/49] target/riscv: add zicntr extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 19/49] Add epmp to extensions list and rename it to smepmp, Alistair Francis, 2023/11/06
- [PULL 23/49] target/riscv/kvm: add zicntr reg, Alistair Francis, 2023/11/06
- [PULL 24/49] target/riscv: add zihpm extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 25/49] target/riscv/kvm: add zihpm reg, Alistair Francis, 2023/11/06
- [PULL 26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot, Alistair Francis, 2023/11/06
- [PULL 27/49] target/riscv: correct csr_ops[CSR_MSECCFG], Alistair Francis, 2023/11/06
- [PULL 28/49] MAINTAINERS: update mail address for Weiwei Li, Alistair Francis, 2023/11/06
- [PULL 31/49] target/riscv: Add cfg property for Zvkb extension,
Alistair Francis <=
- [PULL 30/49] target/riscv: Expose Zvkt extension property, Alistair Francis, 2023/11/06
- [PULL 32/49] target/riscv: Replace Zvbb checking by Zvkb, Alistair Francis, 2023/11/06
- [PULL 29/49] target/riscv: Add cfg property for Zvkt extension, Alistair Francis, 2023/11/06
- [PULL 33/49] target/riscv: Expose Zvkb extension property, Alistair Francis, 2023/11/06
- [PULL 34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 37/49] target/riscv: Expose Zvks[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions, Alistair Francis, 2023/11/06
- [PULL 39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format, Alistair Francis, 2023/11/06