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[PULL 03/49] target/riscv: rename ext_icbom to ext_zicbom
From: |
Alistair Francis |
Subject: |
[PULL 03/49] target/riscv: rename ext_icbom to ext_zicbom |
Date: |
Tue, 7 Nov 2023 12:28:59 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Add a leading 'z' to improve grepping. When one wants to search for uses
of zicbom they're more likely to do 'grep -i zicbom' than 'grep -i
icbom'.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231012164604.398496-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 2 +-
hw/riscv/virt.c | 2 +-
target/riscv/cpu.c | 6 +++---
target/riscv/kvm/kvm-cpu.c | 6 +++---
target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 ++++----
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 9ea30da7e0..e6bef0070f 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -63,7 +63,7 @@ struct RISCVCPUConfig {
bool ext_zkt;
bool ext_zifencei;
bool ext_zicsr;
- bool ext_icbom;
+ bool ext_zicbom;
bool ext_icboz;
bool ext_zicond;
bool ext_zihintntl;
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9de578c756..54e0fe8ecc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -263,7 +263,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
- if (cpu_ptr->cfg.ext_icbom) {
+ if (cpu_ptr->cfg.ext_zicbom) {
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
cpu_ptr->cfg.cbom_blocksize);
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 566b7545e8..943d5ecbfb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -76,7 +76,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD,
RVV,
* instead.
*/
const RISCVIsaExtData isa_edata_arr[] = {
- ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
+ ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
@@ -497,7 +497,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_zicsr = true;
cpu->cfg.pmp = true;
- cpu->cfg.ext_icbom = true;
+ cpu->cfg.ext_zicbom = true;
cpu->cfg.cbom_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
cpu->cfg.ext_icboz = true;
@@ -1284,7 +1284,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
- MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
+ MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 26e68c7ab4..4d4c17fd77 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -213,7 +213,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu,
CPUState *cs)
.kvm_reg_id = _reg_id}
static KVMCPUConfig kvm_multi_ext_cfgs[] = {
- KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM),
+ KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
@@ -804,7 +804,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
}
- if (cpu->cfg.ext_icbom) {
+ if (cpu->cfg.ext_zicbom) {
kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
}
@@ -897,7 +897,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu,
KVMScratchCPU *kvmcpu)
kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
}
- if (cpu->cfg.ext_icbom) {
+ if (cpu->cfg.ext_zicbom) {
kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
}
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc
b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index e5a7704f54..e6ed548376 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -16,10 +16,10 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#define REQUIRE_ZICBOM(ctx) do { \
- if (!ctx->cfg_ptr->ext_icbom) { \
- return false; \
- } \
+#define REQUIRE_ZICBOM(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zicbom) { \
+ return false; \
+ } \
} while (0)
#define REQUIRE_ZICBOZ(ctx) do { \
--
2.41.0
- [PULL 00/49] riscv-to-apply queue, Alistair Francis, 2023/11/06
- [PULL 01/49] target/riscv: rename ext_ifencei to ext_zifencei, Alistair Francis, 2023/11/06
- [PULL 02/49] target/riscv: rename ext_icsr to ext_zicsr, Alistair Francis, 2023/11/06
- [PULL 03/49] target/riscv: rename ext_icbom to ext_zicbom,
Alistair Francis <=
- [PULL 04/49] target/riscv: rename ext_icboz to ext_zicboz, Alistair Francis, 2023/11/06
- [PULL 05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie., Alistair Francis, 2023/11/06
- [PULL 06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST., Alistair Francis, 2023/11/06
- [PULL 07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, Alistair Francis, 2023/11/06
- [PULL 08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Alistair Francis, 2023/11/06
- [PULL 09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 12/49] docs/system/riscv: update 'virt' machine core limit, Alistair Francis, 2023/11/06
- [PULL 13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters(), Alistair Francis, 2023/11/06
- [PULL 11/49] linux-user/riscv: change default cpu to 'max', Alistair Francis, 2023/11/06