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Re: [PATCH 1/1] target/riscv: correct csr_ops[CSR_MSECCFG]
From: |
Alistair Francis |
Subject: |
Re: [PATCH 1/1] target/riscv: correct csr_ops[CSR_MSECCFG] |
Date: |
Mon, 30 Oct 2023 12:13:23 +1000 |
On Sun, Oct 29, 2023 at 10:47 AM Heinrich Schuchardt
<heinrich.schuchardt@canonical.com> wrote:
>
> The CSR register mseccfg is used by multiple extensions: Smepm and Zkr.
>
> Consider this when checking the existence of the register.
>
> Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
sending a v2?
Alistair
> ---
> target/riscv/csr.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4b4ab56c40..07c0cfb7d8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -523,11 +523,14 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> -static RISCVException epmp(CPURISCVState *env, int csrno)
> +static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
> {
> if (riscv_cpu_cfg(env)->epmp) {
> return RISCV_EXCP_NONE;
> }
> + if (riscv_cpu_cfg(env)->ext_zkr) {
> + return RISCV_EXCP_NONE;
> + }
>
> return RISCV_EXCP_ILLEGAL_INST;
> }
> @@ -4379,7 +4382,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph
> },
>
> /* Physical Memory Protection */
> - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
> + [CSR_MSECCFG] = { "mseccfg", have_mseccfg, read_mseccfg,
> write_mseccfg,
> .min_priv_ver = PRIV_VERSION_1_11_0 },
> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
> --
> 2.40.1
>
>