[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 38/41] hw/net/cadence_gem: use FIELD to describe DESCONF6 register
From: |
Peter Maydell |
Subject: |
[PULL 38/41] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields |
Date: |
Fri, 27 Oct 2023 15:39:39 +0100 |
From: Luc Michel <luc.michel@amd.com>
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231017194422.4124691-9-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/cadence_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 7e6cab71071..dffcc64df25 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -283,7 +283,7 @@ REG32(DESCONF3, 0x288)
REG32(DESCONF4, 0x28c)
REG32(DESCONF5, 0x290)
REG32(DESCONF6, 0x294)
-#define GEM_DESCONF6_64B_MASK (1U << 23)
+ FIELD(DESCONF6, DMA_ADDR_64B, 23, 1)
REG32(DESCONF7, 0x298)
REG32(INT_Q1_STATUS, 0x400)
@@ -1463,7 +1463,7 @@ static void gem_reset(DeviceState *d)
s->regs[R_DESCONF] = 0x02D00111;
s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[R_DESCONF5] = 0x002f2045;
- s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
s->regs[R_INT_Q1_MASK] = 0x00000CE6;
s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
--
2.34.1
- [PULL 25/41] hw/intc/pxa2xx: Convert to Resettable interface, (continued)
- [PULL 25/41] hw/intc/pxa2xx: Convert to Resettable interface, Peter Maydell, 2023/10/27
- [PULL 39/41] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields, Peter Maydell, 2023/10/27
- [PULL 34/41] hw/net/cadence_gem: use FIELD to describe NWCFG register fields, Peter Maydell, 2023/10/27
- [PULL 37/41] hw/net/cadence_gem: use FIELD to describe IRQ register fields, Peter Maydell, 2023/10/27
- [PULL 31/41] hw/net/cadence_gem: use REG32 macro for register definitions, Peter Maydell, 2023/10/27
- [PULL 35/41] hw/net/cadence_gem: use FIELD to describe DMACFG register fields, Peter Maydell, 2023/10/27
- [PULL 27/41] hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init(), Peter Maydell, 2023/10/27
- [PULL 41/41] hw/net/cadence_gem: enforce 32 bits variable size for CRC, Peter Maydell, 2023/10/27
- [PULL 28/41] hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it, Peter Maydell, 2023/10/27
- [PULL 20/41] hw/sd/pxa2xx: Realize sysbus device before accessing it, Peter Maydell, 2023/10/27
- [PULL 38/41] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields,
Peter Maydell <=
- [PULL 21/41] hw/sd/pxa2xx: Do not open-code sysbus_create_simple(), Peter Maydell, 2023/10/27
- [PULL 07/41] target/arm: Move ID_AA64PFR* tests together, Peter Maydell, 2023/10/27
- [PULL 40/41] hw/net/cadence_gem: perform PHY access on write only, Peter Maydell, 2023/10/27
- [PULL 36/41] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields, Peter Maydell, 2023/10/27
- Re: [PULL 00/41] target-arm queue, Stefan Hajnoczi, 2023/10/29
- Re: [PULL 00/41] target-arm queue, Stefan Hajnoczi, 2023/10/31