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[PULL 09/41] target/arm: Fix syndrome for FGT traps on ERET
From: |
Peter Maydell |
Subject: |
[PULL 09/41] target/arm: Fix syndrome for FGT traps on ERET |
Date: |
Fri, 27 Oct 2023 15:39:10 +0100 |
In commit 442c9d682c94fc2 when we converted the ERET, ERETAA, ERETAB
instructions to decodetree, the conversion accidentally lost the
correct setting of the syndrome register when taking a trap because
of the FEAT_FGT HFGITR_EL1.ERET bit. Instead of reporting a correct
full syndrome value with the EC and IL bits, we only reported the low
two bits of the syndrome, because the call to syn_erettrap() got
dropped.
Fix the syndrome values for these traps by reinstating the
syn_erettrap() calls.
Fixes: 442c9d682c94fc2 ("target/arm: Convert ERET, ERETAA, ERETAB to
decodetree")
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231024172438.2990945-1-peter.maydell@linaro.org
---
target/arm/tcg/translate-a64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ad78b8b1202..41484d8ae54 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1606,7 +1606,7 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a)
return false;
}
if (s->fgt_eret) {
- gen_exception_insn_el(s, 0, EXCP_UDEF, 0, 2);
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(0), 2);
return true;
}
dst = tcg_temp_new_i64();
@@ -1633,7 +1633,7 @@ static bool trans_ERETA(DisasContext *s, arg_reta *a)
}
/* The FGT trap takes precedence over an auth trap. */
if (s->fgt_eret) {
- gen_exception_insn_el(s, 0, EXCP_UDEF, a->m ? 3 : 2, 2);
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(a->m ? 3 : 2), 2);
return true;
}
dst = tcg_temp_new_i64();
--
2.34.1
- [PULL 00/41] target-arm queue, Peter Maydell, 2023/10/27
- [PULL 01/41] target/arm: Correct minor errors in Cortex-A710 definition, Peter Maydell, 2023/10/27
- [PULL 04/41] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together, Peter Maydell, 2023/10/27
- [PULL 05/41] target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2, Peter Maydell, 2023/10/27
- [PULL 10/41] hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 06/41] target/arm: Move ID_AA64ISAR* test functions together, Peter Maydell, 2023/10/27
- [PULL 02/41] target/arm: Implement Neoverse N2 CPU model, Peter Maydell, 2023/10/27
- [PULL 08/41] target/arm: Move ID_AA64DFR* feature tests together, Peter Maydell, 2023/10/27
- [PULL 11/41] hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 12/41] hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 09/41] target/arm: Fix syndrome for FGT traps on ERET,
Peter Maydell <=
- [PULL 13/41] hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 16/41] hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 03/41] target/arm: Move feature test functions to their own header, Peter Maydell, 2023/10/27
- [PULL 15/41] hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 18/41] hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 19/41] hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 22/41] hw/pcmcia/pxa2xx: Realize sysbus device before accessing it, Peter Maydell, 2023/10/27
- [PULL 24/41] hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init(), Peter Maydell, 2023/10/27
- [PULL 17/41] hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 30/41] misc/led: LED state is set opposite of what is expected, Peter Maydell, 2023/10/27