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[PATCH 12/29] tcg/i386: Add rexw argument to tcg_out_testi
From: |
Richard Henderson |
Subject: |
[PATCH 12/29] tcg/i386: Add rexw argument to tcg_out_testi |
Date: |
Wed, 25 Oct 2023 17:14:03 -0700 |
Move up above tcg_out_cmp, where it will be used.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 36 ++++++++++++++++--------------------
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 6e8af1fcf6..f4f456a2c0 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1418,6 +1418,19 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel
*l, bool small)
}
}
+/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */
+static void __attribute__((unused))
+tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i, int rexw)
+{
+ if (i <= 0xff && (TCG_TARGET_REG_BITS == 64 || r < 4)) {
+ tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r);
+ tcg_out8(s, i);
+ } else {
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_TESTi, r);
+ tcg_out32(s, i);
+ }
+}
+
static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1,
TCGArg arg2, int const_arg2, int rexw)
{
@@ -1796,23 +1809,6 @@ static void tcg_out_nopn(TCGContext *s, int n)
tcg_out8(s, 0x90);
}
-/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */
-static void __attribute__((unused))
-tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i)
-{
- /*
- * This is used for testing alignment, so we can usually use testb.
- * For i686, we have to use testl for %esi/%edi.
- */
- if (i <= 0xff && (TCG_TARGET_REG_BITS == 64 || r < 4)) {
- tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r);
- tcg_out8(s, i);
- } else {
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r);
- tcg_out32(s, i);
- }
-}
-
typedef struct {
TCGReg base;
int index;
@@ -2080,7 +2076,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
ldst->addrlo_reg = addrlo;
ldst->addrhi_reg = addrhi;
- tcg_out_testi(s, addrlo, a_mask);
+ tcg_out_testi(s, addrlo, a_mask, false);
/* jne slow_path */
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
ldst->label_ptr[0] = s->code_ptr;
@@ -2229,7 +2225,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg
datalo, TCGReg datahi,
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
- tcg_out_testi(s, h.base, 15);
+ tcg_out_testi(s, h.base, 15, false);
tcg_out_jxx(s, JCC_JNE, l1, true);
tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg,
@@ -2357,7 +2353,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg
datalo, TCGReg datahi,
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
- tcg_out_testi(s, h.base, 15);
+ tcg_out_testi(s, h.base, 15, false);
tcg_out_jxx(s, JCC_JNE, l1, true);
tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg,
--
2.34.1
- [PULL 09/94] target/sparc: Partition cpu features, (continued)
- [PULL 09/94] target/sparc: Partition cpu features, Richard Henderson, 2023/10/25
- [PULL 10/94] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/25
- [PATCH 01/29] tcg: Introduce TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PULL 03/94] target/sparc: Avoid helper_raise_exception in helper_st_asi, Richard Henderson, 2023/10/25
- [PULL 07/94] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties, Richard Henderson, 2023/10/25
- [PATCH 03/29] tcg/optimize: Split out do_constant_folding_cond1, Richard Henderson, 2023/10/25
- [PATCH 07/29] tcg/aarch64: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 08/29] tcg/aarch64: Generate TBZ, TBNZ, Richard Henderson, 2023/10/25
- [PULL 05/94] configs: Enable MTTCG for sparc, sparc64, Richard Henderson, 2023/10/25
- [PATCH 10/29] tcg/i386: Pass x86 condition codes to tcg_out_cmov, Richard Henderson, 2023/10/25
- [PATCH 12/29] tcg/i386: Add rexw argument to tcg_out_testi,
Richard Henderson <=
- [PATCH 14/29] tcg/loongarch64: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PULL 14/94] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/25
- [PULL 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/25
- [PULL 18/94] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/25
- [PATCH 19/29] tcg/sparc64: Pass TCGCond to tcg_out_cmp, Richard Henderson, 2023/10/25
- [PATCH 15/29] tcg/mips: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PULL 13/94] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/25
- [PULL 11/94] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/25
- [PULL 12/94] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/25