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[PATCH v3 40/90] target/sparc: Convert remaining v8 coproc insns to deco
From: |
Richard Henderson |
Subject: |
[PATCH v3 40/90] target/sparc: Convert remaining v8 coproc insns to decodetree |
Date: |
Fri, 20 Oct 2023 22:31:08 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 11 +++++++++++
target/sparc/translate.c | 32 ++++++--------------------------
2 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 667067822f..1303df92a7 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -216,3 +216,14 @@ Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11
MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11
MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10
+
+NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
+NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
+
+NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
+NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR
+NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC
+NCP 11 ----- 110100 ----- --------- ----- # v8 STC
+NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR
+NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ
+NCP 11 ----- 110111 ----- --------- ----- # v8 STDC
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 7fd19ff5ee..edd9211572 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4830,8 +4830,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
}
} else if (xop < 0x36) {
goto illegal_insn; /* in decodetree */
- } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
+ } else if (xop == 0x36) {
#ifdef TARGET_SPARC64
+ /* VIS */
int opf = GET_FIELD_SP(insn, 5, 13);
rs1 = GET_FIELD(insn, 13, 17);
rs2 = GET_FIELD(insn, 27, 31);
@@ -5271,14 +5272,11 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
goto illegal_insn;
}
#else
- goto ncp_insn;
-#endif
- } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
-#ifdef TARGET_SPARC64
- goto illegal_insn;
-#else
- goto ncp_insn;
+ g_assert_not_reached(); /* in decodetree */
#endif
+ } else if (xop == 0x37) {
+ /* V8 CPop2, V9 impdep2 */
+ goto illegal_insn; /* in decodetree */
#ifdef TARGET_SPARC64
} else if (xop == 0x39) { /* V9 return */
save_state(dc);
@@ -5494,13 +5492,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = gen_load_gpr(dc, rd);
gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
break;
-
-#ifndef TARGET_SPARC64
- case 0x30: /* ldc */
- case 0x31: /* ldcsr */
- case 0x33: /* lddc */
- goto ncp_insn;
-#endif
#endif
#ifdef TARGET_SPARC64
case 0x08: /* V9 ldsw */
@@ -5761,12 +5752,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src2 = gen_load_gpr(dc, rs2);
gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
break;
-#else
- case 0x34: /* stc */
- case 0x35: /* stcsr */
- case 0x36: /* stdcq */
- case 0x37: /* stdc */
- goto ncp_insn;
#endif
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x3c: /* V9 or LEON3 casa */
@@ -5806,11 +5791,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
return;
#endif
-#ifndef TARGET_SPARC64
- ncp_insn:
- gen_exception(dc, TT_NCP_INSN);
- return;
-#endif
}
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--
2.34.1
- [PATCH v3 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, (continued)
- [PATCH v3 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 22/90] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 24/90] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 29/90] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 32/90] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 37/90] target/sparc: Move SLL, SRL, SRA to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 34/90] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 35/90] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 39/90] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 40/90] target/sparc: Convert remaining v8 coproc insns to decodetree,
Richard Henderson <=
- [PATCH v3 42/90] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 41/90] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 46/90] target/sparc: Split out ldst functions with asi pre-computed, Richard Henderson, 2023/10/21
- [PATCH v3 43/90] target/sparc: Move DONE, RETRY to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 48/90] target/sparc: Move simple integer load/store to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 59/90] target/sparc: Move EDGE* to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 60/90] target/sparc: Move ARRAY* to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 52/90] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 56/90] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree, Richard Henderson, 2023/10/21