RE: [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields

[Boddu, Sai Pavan]

>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe
>[TX|RX]STATUS register fields
>
>Use de FIELD macro to describe the TXSTATUS and RXSTATUS register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>

Reviewed-by: sai.pavan.boddu@amd.com


>---
> hw/net/cadence_gem.c | 34 +++++++++++++++++++++++++---------
> 1 file changed, 25 insertions(+), 9 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>5c386adff2..0acee1d544 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -130,13 +130,34 @@ REG32(DMACFG, 0x10) /* DMA Control reg */
>     FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
>     FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
> #define GEM_DMACFG_RBUFSZ_MUL  64         /* DMA RX Buffer Size multiplier
>*/
>
> REG32(TXSTATUS, 0x14) /* TX Status reg */
>+    FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1)
>+    FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1)
>+    FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1)
>+    FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1)
>+    FIELD(TXSTATUS, RESP_NOT_OK, 8, 1)
>+    FIELD(TXSTATUS, LATE_COLLISION, 7, 1)
>+    FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1)
>+    FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1)
>+    FIELD(TXSTATUS, AMBA_ERROR, 4, 1)
>+    FIELD(TXSTATUS, TRANSMIT_GO, 3, 1)
>+    FIELD(TXSTATUS, RETRY_LIMIT, 2, 1)
>+    FIELD(TXSTATUS, COLLISION, 1, 1)
>+    FIELD(TXSTATUS, USED_BIT_READ, 0, 1)
>+
> REG32(RXQBASE, 0x18) /* RX Q Base address reg */  REG32(TXQBASE, 0x1c) /*
>TX Q Base address reg */  REG32(RXSTATUS, 0x20) /* RX Status reg */
>+    FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1)
>+    FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1)
>+    FIELD(RXSTATUS, RESP_NOT_OK, 3, 1)
>+    FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
>+    FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
>+    FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
>+
> REG32(ISR, 0x24) /* Interrupt Status reg */  REG32(IER, 0x28) /* Interrupt
>Enable reg */  REG32(IDR, 0x2c) /* Interrupt Disable reg */  REG32(IMR, 0x30)
>/* Interrupt Mask reg */  REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
>@@ -284,15 +305,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>     FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
>     FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
>
>-#define GEM_TXSTATUS_TXCMPL    0x00000020 /* Transmit Complete */
>-#define GEM_TXSTATUS_USED      0x00000001 /* sw owned descriptor
>encountered */
>-
>-#define GEM_RXSTATUS_FRMRCVD   0x00000002 /* Frame received */
>-#define GEM_RXSTATUS_NOBUF     0x00000001 /* Buffer unavailable */
>
> /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
> #define GEM_INT_TXCMPL        0x00000080 /* Transmit Complete */
> #define GEM_INT_AMBA_ERR      0x00000040
> #define GEM_INT_TXUSED         0x00000008
>@@ -985,11 +1001,11 @@ static void gem_get_rx_desc(CadenceGEMState *s,
>int q)
>                        sizeof(uint32_t) * gem_get_desc_len(s, true));
>
>     /* Descriptor owned by software ? */
>     if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
>         DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n",
>desc_addr);
>-        s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
>+        s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
>         gem_set_isr(s, q, GEM_INT_RXUSED);
>         /* Handle interrupt consequences */
>         gem_update_int_status(s);
>     }
> }
>@@ -1162,11 +1178,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>     }
>
>     /* Count it */
>     gem_receive_updatestats(s, buf, size);
>
>-    s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
>+    s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
>     gem_set_isr(s, q, GEM_INT_RXCMPL);
>
>     /* Handle interrupt consequences */
>     gem_update_int_status(s);
>
>@@ -1313,11 +1329,11 @@ static void gem_transmit(CadenceGEMState *s)
>                     s->tx_desc_addr[q] = packet_desc_addr +
>                                          4 * gem_get_desc_len(s, false);
>                 }
>                 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
>
>-                s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
>+                s->regs[R_TXSTATUS] |=
>+ R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
>                 gem_set_isr(s, q, GEM_INT_TXCMPL);
>
>                 /* Handle interrupt consequences */
>                 gem_update_int_status(s);
>
>@@ -1361,11 +1377,11 @@ static void gem_transmit(CadenceGEMState *s)
>                                MEMTXATTRS_UNSPECIFIED, desc,
>                                sizeof(uint32_t) * gem_get_desc_len(s, false));
>         }
>
>         if (tx_desc_get_used(desc)) {
>-            s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
>+            s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
>             /* IRQ TXUSED is defined only for queue 0 */
>             if (q == 0) {
>                 gem_set_isr(s, 0, GEM_INT_TXUSED);
>             }
>             gem_update_int_status(s);
>--
>2.39.2