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Re: [PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num" |
Date: |
Mon, 16 Oct 2023 14:29:17 +1000 |
On Fri, Oct 13, 2023 at 11:32 PM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> Using a mask instead of the number of PMU devices supports the accurate
> emulation of platforms that have a discontinuous set of PMU counters.
>
> Generate a warning if the old property changed from the default but
> still go ahead and use it to generate the mask if the user has changed
> it from the default
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> ---
> target/riscv/cpu.c | 5 +++--
> target/riscv/cpu_cfg.h | 3 ++-
> target/riscv/machine.c | 2 +-
> target/riscv/pmu.c | 20 ++++++++++++++++----
> 4 files changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c9d8fc12fe..420673b491 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1487,7 +1487,7 @@ static void riscv_cpu_realize_tcg(DeviceState *dev,
> Error **errp)
> riscv_timer_init(cpu);
> }
>
> - if (cpu->cfg.pmu_num) {
> + if (cpu->cfg.pmu_mask) {
> riscv_pmu_init(cpu, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> @@ -1812,7 +1812,8 @@ static void riscv_cpu_add_misa_properties(Object
> *cpu_obj)
>
> static Property riscv_cpu_extensions[] = {
> /* Defaults for standard extensions */
> - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
> + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), /* Deprecated */
This will need to be rebased.
You could probably use riscv_cpu_deprecated_exts, but then you also
need to modify cpu_set_multi_ext_cfg()
> + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask,
> MAKE_64BIT_MASK(3, 16)),
> DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 0e6a0f245c..d273487040 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -123,7 +123,8 @@ struct RISCVCPUConfig {
> bool ext_xtheadsync;
> bool ext_XVentanaCondOps;
>
> - uint8_t pmu_num;
> + uint8_t pmu_num; /* Deprecated */
> + uint32_t pmu_mask;
> char *priv_spec;
> char *user_spec;
> char *bext_spec;
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index c7c862cdd3..9f6e3f7a6d 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -313,7 +313,7 @@ static bool pmu_needed(void *opaque)
> {
> RISCVCPU *cpu = opaque;
>
> - return cpu->cfg.pmu_num;
> + return (cpu->cfg.pmu_mask > 0);
> }
>
> static const VMStateDescription vmstate_pmu_ctr_state = {
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index 7ddf4977b1..9253e5f17a 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -18,6 +18,7 @@
>
> #include "qemu/osdep.h"
> #include "qemu/log.h"
> +#include "qemu/error-report.h"
> #include "cpu.h"
> #include "pmu.h"
> #include "sysemu/cpu-timers.h"
> @@ -184,7 +185,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum
> riscv_pmu_event_idx event_idx)
> CPURISCVState *env = &cpu->env;
> gpointer value;
>
> - if (!cpu->cfg.pmu_num) {
> + if (!cpu->cfg.pmu_mask) {
> return 0;
> }
> value = g_hash_table_lookup(cpu->pmu_event_ctr_map,
> @@ -434,7 +435,13 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp)
> {
> uint8_t pmu_num = cpu->cfg.pmu_num;
>
> - if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) {
> + if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) {
> + error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set");
> + return;
> + }
> +
> + if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3) ||
> + (pmu_num > RV_MAX_MHPMCOUNTERS - 3)) {
> error_setg(errp, "Number of counters exceeds maximum available");
> return;
> }
> @@ -445,6 +452,11 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> - /* Create a bitmask of available programmable counters */
> - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num);
> + /* Check if user set it by comparing against default */
> + if (pmu_num != 16) {
This won't work if the user sets 16 though
Alistair
> + warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\"");
> + cpu->cfg.pmu_mask = MAKE_32BIT_MASK(3, pmu_num);
> + }
> +
> + cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask;
> }
> --
> 2.41.0
>
>
- [PATCH v3 0/6] Support discontinuous PMU counters, Rob Bradford, 2023/10/13
- [PATCH v3 1/6] target/riscv: Propagate error from PMU setup, Rob Bradford, 2023/10/13
- [PATCH v3 3/6] target/riscv: Use existing PMU counter mask in FDT generation, Rob Bradford, 2023/10/13
- [PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num", Rob Bradford, 2023/10/13
- Re: [PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num",
Alistair Francis <=
- [PATCH v3 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro, Rob Bradford, 2023/10/13
- [PATCH v3 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation, Rob Bradford, 2023/10/13
- [PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous, Rob Bradford, 2023/10/13