[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree |
Date: |
Fri, 13 Oct 2023 14:28:09 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 8 ++++++--
target/sparc/translate.c | 14 ++++++++++----
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 1a641248ce..c032b81c16 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -225,6 +225,9 @@ RESTORE 10 ..... 111101 ..... . .............
@r_r_ri
DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000
+NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
+NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
+
##
## Major Opcode 11 -- load and store instructions
##
@@ -293,8 +296,9 @@ CASA 11 ..... 111100 ..... . .............
@casa_imm
CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi
CASXA 11 ..... 111110 ..... . ............. @casa_imm
-NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
-NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
+NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH
+NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH
+NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA
NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index beb42b9fb7..02030bd99b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4055,6 +4055,14 @@ static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
return false;
}
+static bool trans_NOP_v9(DisasContext *dc, arg_NOP_v9 *a)
+{
+ if (avail_64(dc)) {
+ return advance_pc(dc);
+ }
+ return false;
+}
+
static bool do_cc_arith(DisasContext *dc, arg_r_r_ri *a, int cc_op,
void (*func)(TCGv, TCGv, TCGv),
void (*funci)(TCGv, TCGv, target_long))
@@ -5468,10 +5476,10 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x0b: /* V9 ldx */
case 0x18: /* V9 ldswa */
case 0x1b: /* V9 ldxa */
+ case 0x2d: /* V9 prefetch */
+ case 0x3d: /* V9 prefetcha */
goto illegal_insn; /* in decodetree */
#ifdef TARGET_SPARC64
- case 0x2d: /* V9 prefetch, no effect */
- goto skip_move;
case 0x30: /* V9 ldfa */
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
@@ -5486,8 +5494,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
gen_update_fprs_dirty(dc, DFPREG(rd));
goto skip_move;
- case 0x3d: /* V9 prefetcha, no effect */
- goto skip_move;
case 0x32: /* V9 ldqfa */
CHECK_FPU_FEATURE(dc, FLOAT128);
if (gen_trap_ifnofpu(dc)) {
--
2.34.1
- [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN to decodetree, (continued)
- [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/13
- [PATCH 38/85] target/sparc: Move DONE, RETRY to decodetree, Richard Henderson, 2023/10/13
- [PATCH 39/85] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/13
- [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX, Richard Henderson, 2023/10/13
- [PATCH 44/85] target/sparc: Move asi integer load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed, Richard Henderson, 2023/10/13
- [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends, Richard Henderson, 2023/10/13
- [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 46/85] target/sparc: Move SWAP, SWAPA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree,
Richard Henderson <=
- [PATCH 51/85] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 47/85] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 52/85] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations, Richard Henderson, 2023/10/13
- [PATCH 54/85] target/sparc: Move EDGE* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 56/85] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 57/85] target/sparc: Move BMASK to decodetree, Richard Henderson, 2023/10/13
- [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}*, Richard Henderson, 2023/10/13
- [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed, Richard Henderson, 2023/10/13