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[PATCH v4 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext i
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From: |
Rajnesh Kanwal |
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Subject: |
[PATCH v4 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled |
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Date: |
Thu, 12 Oct 2023 11:01:00 +0100 |
With H-Ext supported, VS bits are all hardwired to one in MIDELEG
denoting always delegated interrupts. This is being done in rmw_mideleg
but given mideleg is used in other places when routing interrupts
this change initializes it in riscv_cpu_realize to be on the safe side.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a28918ab30..34e034b9f3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -618,7 +618,12 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
riscv_pmu_timer_cb, cpu);
}
- }
+ }
+
+ /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */
+ if (riscv_has_ext(env, RVH)) {
+ env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP;
+ }
#endif
return true;
--
2.34.1
- [PATCH v4 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support, Rajnesh Kanwal, 2023/10/12
- [PATCH v4 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie., Rajnesh Kanwal, 2023/10/12
- [PATCH v4 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST., Rajnesh Kanwal, 2023/10/12
- [PATCH v4 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled,
Rajnesh Kanwal <=
- [PATCH v4 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/10/12
- [PATCH v4 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/10/12
- [PATCH v4 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Rajnesh Kanwal, 2023/10/12