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[PULL 11/20] swim: add trace events for IWM and ISM registers
From: |
Laurent Vivier |
Subject: |
[PULL 11/20] swim: add trace events for IWM and ISM registers |
Date: |
Sun, 8 Oct 2023 08:23:40 +0200 |
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20231004083806.757242-12-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/block/swim.c | 14 ++++++++++++++
hw/block/trace-events | 7 +++++++
2 files changed, 21 insertions(+)
diff --git a/hw/block/swim.c b/hw/block/swim.c
index 333da08ce093..7df36ea139cb 100644
--- a/hw/block/swim.c
+++ b/hw/block/swim.c
@@ -19,6 +19,7 @@
#include "hw/block/block.h"
#include "hw/block/swim.h"
#include "hw/qdev-properties.h"
+#include "trace.h"
/* IWM registers */
@@ -125,6 +126,13 @@
#define SWIM_HEDSEL 0x20
#define SWIM_MOTON 0x80
+static const char *swim_reg_names[] = {
+ "WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER",
+ "WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1",
+ "READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER",
+ "READ_PHASE", "READ_SETUP", "READ_STATUS", "READ_HANDSHAKE"
+};
+
static void fd_recalibrate(FDrive *drive)
{
}
@@ -267,6 +275,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg,
uint64_t value,
reg >>= REG_SHIFT;
swimctrl->regs[reg >> 1] = reg & 1;
+ trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1));
if (swimctrl->regs[IWM_Q6] &&
swimctrl->regs[IWM_Q7]) {
@@ -297,6 +306,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg,
uint64_t value,
if (value == 0x57) {
swimctrl->mode = SWIM_MODE_SWIM;
swimctrl->iwm_switch = 0;
+ trace_swim_iwm_switch();
}
break;
}
@@ -312,6 +322,7 @@ static uint64_t iwmctrl_read(void *opaque, hwaddr reg,
unsigned size)
swimctrl->regs[reg >> 1] = reg & 1;
+ trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1));
return 0;
}
@@ -327,6 +338,8 @@ static void swimctrl_write(void *opaque, hwaddr reg,
uint64_t value,
reg >>= REG_SHIFT;
+ trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value);
+
switch (reg) {
case SWIM_WRITE_PHASE:
swimctrl->swim_phase = value;
@@ -376,6 +389,7 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg,
unsigned size)
break;
}
+ trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value);
return value;
}
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 34be8b9135f5..c041ec45e312 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -90,3 +90,10 @@ m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p]
Read data 0x%"PRIx32"=0
m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP
0x%"PRIx32"=0x%"PRIx8
m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
+
+# swim.c
+swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value)
"reg=%d [%s] size=%u value=0x%"PRIx64
+swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value)
"reg=%d [%s] size=%u value=0x%"PRIx64
+swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u
value=0x%"PRIx64
+swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u
value=0x%"PRIx64
+swim_iwm_switch(void) "switch from IWM to SWIM mode"
--
2.41.0
- [PULL 04/20] q800: implement additional machine id bits on VIA1 port A, (continued)
- [PULL 04/20] q800: implement additional machine id bits on VIA1 port A, Laurent Vivier, 2023/10/08
- [PULL 02/20] q800: add djMEMC memory controller, Laurent Vivier, 2023/10/08
- [PULL 01/20] q800-glue.c: convert to Resettable interface, Laurent Vivier, 2023/10/08
- [PULL 05/20] q800: add IOSB subsystem, Laurent Vivier, 2023/10/08
- [PULL 06/20] q800: allow accesses to RAM area even if less memory is available, Laurent Vivier, 2023/10/08
- [PULL 08/20] asc: generate silence if FIFO empty but engine still running, Laurent Vivier, 2023/10/08
- [PULL 03/20] q800: add machine id register, Laurent Vivier, 2023/10/08
- [PULL 07/20] audio: add Apple Sound Chip (ASC) emulation, Laurent Vivier, 2023/10/08
- [PULL 09/20] q800: add Apple Sound Chip (ASC) audio to machine, Laurent Vivier, 2023/10/08
- [PULL 10/20] q800: add easc bool machine class property to switch between ASC and EASC, Laurent Vivier, 2023/10/08
- [PULL 11/20] swim: add trace events for IWM and ISM registers,
Laurent Vivier <=
- [PULL 12/20] swim: split into separate IWM and ISM register blocks, Laurent Vivier, 2023/10/08
- [PULL 13/20] swim: update IWM/ISM register block decoding, Laurent Vivier, 2023/10/08
- [PULL 14/20] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK, Laurent Vivier, 2023/10/08
- [PULL 15/20] mac_via: workaround NetBSD ADB bus enumeration issue, Laurent Vivier, 2023/10/08
- [PULL 16/20] mac_via: implement ADB_STATE_IDLE state if shift register in input mode, Laurent Vivier, 2023/10/08
- [PULL 18/20] q800: add ESCC alias at 0xc000, Laurent Vivier, 2023/10/08
- [PULL 17/20] mac_via: always clear ADB interrupt when switching to A/UX mode, Laurent Vivier, 2023/10/08
- [PULL 20/20] mac_via: extend timer calibration hack to work with A/UX, Laurent Vivier, 2023/10/08
- [PULL 19/20] q800: add alias for MacOS toolbox ROM at 0x40000000, Laurent Vivier, 2023/10/08
- Re: [PULL 00/20] Q800 for 8.2 patches, Stefan Hajnoczi, 2023/10/09