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[PATCH v2 07/10] target/riscv/tcg: add MISA user options hash
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 07/10] target/riscv/tcg: add MISA user options hash |
Date: |
Fri, 6 Oct 2023 10:21:31 -0300 |
We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.
Profile support requires tne need to check for user choice for MISA
extensions, so let's add the corresponding hash now. It works like the
existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits
options in the cpu_set_misa_ext_cfg() callback.
Note that we can't re-use the same hash from multi-letter extensions
because that hash uses cpu->cfg offsets as keys, while for MISA
extensions we're using MISA bits as keys.
After adding the user hash in cpu_set_misa_ext_cfg(), setting default
values with object_property_set_bool() in add_misa_properties() will end
up marking the user choice hash with them. Set the default value
manually to avoid it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 8fb77e9e35..58de4428a9 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -34,6 +34,7 @@
/* Hash that stores user set extensions */
static GHashTable *multi_ext_user_opts;
+static GHashTable *misa_ext_user_opts;
static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
{
@@ -689,6 +690,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v,
const char *name,
return;
}
+ g_hash_table_insert(misa_ext_user_opts,
+ GUINT_TO_POINTER(misa_bit),
+ (gpointer)value);
+
prev_val = env->misa_ext & misa_bit;
if (value == prev_val) {
@@ -752,6 +757,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
*/
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
{
+ CPURISCVState *env = &RISCV_CPU(cpu_obj)->env;
bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
int i;
@@ -772,7 +778,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
NULL, (void *)misa_cfg);
object_property_set_description(cpu_obj, name, desc);
if (use_def_vals) {
- object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+ if (misa_cfg->enabled) {
+ env->misa_ext |= bit;
+ env->misa_ext_mask |= bit;
+ } else {
+ env->misa_ext &= ~bit;
+ env->misa_ext_mask &= ~bit;
+ }
}
}
}
@@ -967,6 +979,7 @@ static void tcg_cpu_instance_init(CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
Object *obj = OBJECT(cpu);
+ misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
riscv_cpu_add_user_properties(obj);
--
2.41.0
- [PATCH v2 00/10] riscv: RVA22U64 profile support, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 01/10] target/riscv/cpu.c: add zicntr extension flag, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 02/10] target/riscv/cpu.c: add zihpm extension flag, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 03/10] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 07/10] target/riscv/tcg: add MISA user options hash,
Daniel Henrique Barboza <=
- [PATCH v2 04/10] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 08/10] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 05/10] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 06/10] target/riscv/tcg: commit profiles during realize(), Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 09/10] target/riscv/tcg: handle MISA bits on profile commit, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 10/10] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/10/06
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Alistair Francis, 2023/10/10