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Re: [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval
From: |
Jonathan Cameron |
Subject: |
Re: [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval |
Date: |
Wed, 27 Sep 2023 14:55:14 +0100 |
...
> +/* CXL r3.0 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */
> +static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
> + uint8_t *payload_in,
> + size_t len_in,
> + uint8_t *payload_out,
> + size_t *len_out,
> + CXLCCI *cci)
> +{
> + /* CXL r3.0 Table 7-18: Get Physical Port State Request Payload */
> + struct cxl_fmapi_get_phys_port_state_req_pl {
> + uint8_t num_ports;
> + uint8_t ports[];
> + } QEMU_PACKED *in;
> +
> + /*
> + * CXL r3.0 Table 7-20: Get Physical Port State Port Information Block
> + * Format
> + */
> + struct cxl_fmapi_port_state_info_block {
> + uint8_t port_id;
> + uint8_t config_state;
> + uint8_t connected_device_cxl_version;
> + uint8_t rsv1;
> + uint8_t connected_device_type;
> + uint8_t port_cxl_version_bitmask;
> + uint8_t max_link_width;
> + uint8_t negotiated_link_width;
> + uint8_t supported_link_speeds_vector;
> + uint8_t max_link_speed;
> + uint8_t current_link_speed;
> + uint8_t ltssm_state;
> + uint8_t first_lane_num;
> + uint16_t link_state;
> + uint8_t supported_ld_count;
> + } QEMU_PACKED;
> +
> + /* CXL r3.0 Table 7-19: Get Physical Port State Response Payload */
> + struct cxl_fmapi_get_phys_port_state_resp_pl {
> + uint8_t num_ports;
> + uint8_t rsv1[3];
> + struct cxl_fmapi_port_state_info_block ports[];
> + } QEMU_PACKED *out;
...
> +
> + pl_size = sizeof(out) + sizeof(*out->ports) * in->num_ports;
In cleaning up up my tests I added a missing check on the pl size.
First term should be sizeof(*out)
> +
> + *len_out = pl_size;
> +
> + return CXL_MBOX_SUCCESS;
> +}
> +
- Re: [PATCH 04/19] hw/cxl/mbox: Generalize the CCI command processing, (continued)
- [PATCH 05/19] hw/pci-bridge/cxl_upstream: Move defintion of device to header., Jonathan Cameron, 2023/09/25
- [PATCH 06/19] hw/cxl/i2c_mctp_cxl: Initial device emulation, Jonathan Cameron, 2023/09/25
- [PATCH 07/19] hw/cxl/mbox: Add Information and Status / Identify command, Jonathan Cameron, 2023/09/25
- [PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs, Jonathan Cameron, 2023/09/25
- [PATCH 09/19] hw/cxl/mbox: Add Physical Switch Identify command., Jonathan Cameron, 2023/09/25
- [PATCH 10/19] hw/cxl: Add a switch mailbox CCI function, Jonathan Cameron, 2023/09/25
- [PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and link speed, Jonathan Cameron, 2023/09/25
- [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval, Jonathan Cameron, 2023/09/25
- Re: [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval,
Jonathan Cameron <=
- [PATCH 13/19] hw/cxl/mbox: Add Get Background Operation Status Command, Jonathan Cameron, 2023/09/25
- [PATCH 14/19] hw/cxl/mbox: Add support for background operations, Jonathan Cameron, 2023/09/25
- [PATCH 15/19] hw/cxl/mbox: Wire up interrupts for background completion, Jonathan Cameron, 2023/09/25
- [PATCH 16/19] hw/cxl: Add support for device sanitation, Jonathan Cameron, 2023/09/25
- [PATCH 17/19] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions, Jonathan Cameron, 2023/09/25
- [PATCH 18/19] hw/cxl: Add dummy security state get, Jonathan Cameron, 2023/09/25
- [PATCH 19/19] hw/cxl: Add tunneled command support to mailbox for switch cci/mctp., Jonathan Cameron, 2023/09/25
- Re: [PATCH 00/19] QEMU: CXL mailbox rework and features, Jonathan Cameron, 2023/09/25
- Re: [PATCH 00/19] QEMU: CXL mailbox rework and features, Gregory Price, 2023/09/28