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Re: [RESEND] qemu/timer: Add host ticks function for RISC-V


From: LIU Zhiwei
Subject: Re: [RESEND] qemu/timer: Add host ticks function for RISC-V
Date: Mon, 11 Sep 2023 13:56:15 +0800
User-agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0


On 2023/9/9 22:45, Palmer Dabbelt wrote:
On Sat, 09 Sep 2023 00:18:02 PDT (-0700), pbonzini@redhat.com wrote:
Il sab 9 set 2023, 03:35 Atish Patra <atishp@atishpatra.org> ha scritto:

On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Queued, thanks.
>

I didn't realize it was already queued. Gmail threads failed me this time.
@Paolo Bonzini : Can you please drop this one as this will break as
soon as the host riscv system
has the latest kernel ? I have provided more details in the original
thread.

https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg01941.html


If you have dynamic clock adjustment, does rdcycle increase with a fixed
frequency or does it provide the raw number of clock cycles? If the latter, I agree that it should be provided by perf; but if the frequency is fixed
then it would be the same as rdtsc on Intel.

That really depends on exactly how the system is set up, but there are systems for which the rdcycle frequency changes when clock speeds change and thus will produce surprising answers for users trying to use rdcycle as a RTC.  We have rdtime for that, but it has other problems (it's trapped and emulated in M-mode on some systems, so it's slow and noisy).

So we're steering folks towards perf where we can, as at least that way we've got a higher-level interface we can use to describe these quirks.

OK. I will send a v2 patch using rdtime.

Thanks,
Zhiwei



Paolo



> Paolo
>
>


--
Regards,
Atish





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