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[PULL 40/65] linux-user/riscv: Add new extensions to hwprobe
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From: |
Alistair Francis |
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Subject: |
[PULL 40/65] linux-user/riscv: Add new extensions to hwprobe |
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Date: |
Fri, 8 Sep 2023 16:04:06 +1000 |
From: Robbin Ehn <rehn@rivosinc.com>
This patch adds the new extensions in
linux 6.5 to the hwprobe syscall.
And fixes RVC check to OR with correct value.
The previous variable contains 0 therefore it
did work.
Signed-off-by: Robbin Ehn <rehn@rivosinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <bc82203b72d7efb30f1b4a8f9eb3d94699799dc8.camel@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
linux-user/syscall.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index dac0641bab..3521a2d70b 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8793,6 +8793,10 @@ static int do_getdents64(abi_long dirfd, abi_long arg2,
abi_long count)
#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
#define RISCV_HWPROBE_IMA_FD (1 << 0)
#define RISCV_HWPROBE_IMA_C (1 << 1)
+#define RISCV_HWPROBE_IMA_V (1 << 2)
+#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
+#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
+#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
@@ -8840,7 +8844,15 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
riscv_has_ext(env, RVD) ?
RISCV_HWPROBE_IMA_FD : 0;
value |= riscv_has_ext(env, RVC) ?
- RISCV_HWPROBE_IMA_C : pair->value;
+ RISCV_HWPROBE_IMA_C : 0;
+ value |= riscv_has_ext(env, RVV) ?
+ RISCV_HWPROBE_IMA_V : 0;
+ value |= cfg->ext_zba ?
+ RISCV_HWPROBE_EXT_ZBA : 0;
+ value |= cfg->ext_zbb ?
+ RISCV_HWPROBE_EXT_ZBB : 0;
+ value |= cfg->ext_zbs ?
+ RISCV_HWPROBE_EXT_ZBS : 0;
__put_user(value, &pair->value);
break;
case RISCV_HWPROBE_KEY_CPUPERF_0:
--
2.41.0
- [PULL 31/65] target/riscv: Create an KVM AIA irqchip, (continued)
- [PULL 31/65] target/riscv: Create an KVM AIA irqchip, Alistair Francis, 2023/09/08
- [PULL 32/65] target/riscv: update APLIC and IMSIC to support KVM AIA, Alistair Francis, 2023/09/08
- [PULL 33/65] target/riscv: select KVM AIA in riscv virt machine, Alistair Francis, 2023/09/08
- [PULL 34/65] hw/riscv: virt: Fix riscv,pmu DT node path, Alistair Francis, 2023/09/08
- [PULL 35/65] target/riscv: Update CSR bits name for svadu extension, Alistair Francis, 2023/09/08
- [PULL 36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/08
- [PULL 37/65] riscv: zicond: make non-experimental, Alistair Francis, 2023/09/08
- [PULL 38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 39/65] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 42/65] target/riscv: Allocate itrigger timers only once, Alistair Francis, 2023/09/08
- [PULL 40/65] linux-user/riscv: Add new extensions to hwprobe,
Alistair Francis <=
- [PULL 41/65] target/riscv: Use accelerated helper for AES64KS1I, Alistair Francis, 2023/09/08
- [PULL 43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes, Alistair Francis, 2023/09/08
- [PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec, Alistair Francis, 2023/09/08
- [PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64, Alistair Francis, 2023/09/08
- [PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, Alistair Francis, 2023/09/08
- [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper, Alistair Francis, 2023/09/08