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[PATCH v4 25/48] target/loognarch: Implement xvldi
From: |
Song Gao |
Subject: |
[PATCH v4 25/48] target/loognarch: Implement xvldi |
Date: |
Wed, 30 Aug 2023 16:48:39 +0800 |
This patch includes:
- XVLDI.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/insns.decode | 2 ++
target/loongarch/disas.c | 7 +++++++
target/loongarch/insn_trans/trans_lasx.c.inc | 2 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 6 ++++--
4 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 6a161d6d20..edaa756395 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1605,6 +1605,8 @@ xvmskltz_d 0111 01101001 11000 10011 ..... .....
@vv
xvmskgez_b 0111 01101001 11000 10100 ..... ..... @vv
xvmsknz_b 0111 01101001 11000 11000 ..... ..... @vv
+xvldi 0111 01111110 00 ............. ..... @v_i13
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 1a11153343..8fa2edf007 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1703,6 +1703,11 @@ static bool trans_##insn(DisasContext *ctx, arg_##type *
a) \
return true; \
}
+static void output_v_i_x(DisasContext *ctx, arg_v_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "x%d, 0x%x", a->vd, a->imm);
+}
+
static void output_vvv_x(DisasContext *ctx, arg_vvv * a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, x%d", a->vd, a->vj, a->vk);
@@ -2022,6 +2027,8 @@ INSN_LASX(xvsigncov_h, vvv)
INSN_LASX(xvsigncov_w, vvv)
INSN_LASX(xvsigncov_d, vvv)
+INSN_LASX(xvldi, v_i)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 92fae91900..f0e71f5f98 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -351,6 +351,8 @@ TRANS(xvmskltz_d, LASX, gen_vv, 32, gen_helper_vmskltz_d)
TRANS(xvmskgez_b, LASX, gen_vv, 32, gen_helper_vmskgez_b)
TRANS(xvmsknz_b, LASX, gen_vv, 32, gen_helper_vmsknz_b)
+TRANS(xvldi, LASX, do_vldi, 32)
+
TRANS(xvreplgr2vr_b, LASX, gvec_dup, 32, MO_8)
TRANS(xvreplgr2vr_h, LASX, gvec_dup, 32, MO_16)
TRANS(xvreplgr2vr_w, LASX, gvec_dup, 32, MO_32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 7e77686bfc..f76da508c3 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -3068,7 +3068,7 @@ static uint64_t vldi_get_value(DisasContext *ctx,
uint32_t imm)
return data;
}
-static bool trans_vldi(DisasContext *ctx, arg_vldi *a)
+static bool do_vldi(DisasContext *ctx, arg_vldi *a, uint32_t oprsz)
{
int sel, vece;
uint64_t value;
@@ -3089,11 +3089,13 @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a)
vece = (a->imm >> 10) & 0x3;
}
- tcg_gen_gvec_dup_i64(vece, vec_full_offset(a->vd), 16, ctx->vl/8,
+ tcg_gen_gvec_dup_i64(vece, vec_full_offset(a->vd), oprsz, ctx->vl / 8,
tcg_constant_i64(value));
return true;
}
+TRANS(vldi, LSX, do_vldi, 16)
+
TRANS(vand_v, LSX, gvec_vvv, 16, MO_64, tcg_gen_gvec_and)
TRANS(vor_v, LSX, gvec_vvv, 16, MO_64, tcg_gen_gvec_or)
TRANS(vxor_v, LSX, gvec_vvv, 16, MO_64, tcg_gen_gvec_xor)
--
2.39.1
- [PATCH v4 18/48] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}, (continued)
- [PATCH v4 18/48] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}, Song Gao, 2023/08/30
- [PATCH v4 20/48] target/loongarch: Implement xvsat, Song Gao, 2023/08/30
- [PATCH v4 22/48] target/loongarch: Implement vext2xv, Song Gao, 2023/08/30
- [PATCH v4 24/48] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz, Song Gao, 2023/08/30
- [PATCH v4 21/48] target/loongarch: Implement xvexth, Song Gao, 2023/08/30
- [PATCH v4 25/48] target/loognarch: Implement xvldi,
Song Gao <=
- [PATCH v4 26/48] target/loongarch: Implement LASX logic instructions, Song Gao, 2023/08/30
- [PATCH v4 23/48] target/loongarch: Implement xvsigncov, Song Gao, 2023/08/30
- [PATCH v4 27/48] target/loongarch: Implement xvsll xvsrl xvsra xvrotr, Song Gao, 2023/08/30
- [PATCH v4 31/48] target/loongarch: Implement xvsrlrn xvsrarn, Song Gao, 2023/08/30
- [PATCH v4 30/48] target/loongarch: Implement xvsrln xvsran, Song Gao, 2023/08/30
- [PATCH v4 36/48] target/loongarch: Implement xvbitclr xvbitset xvbitrev, Song Gao, 2023/08/30