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[PULL 20/35] target/arm/ptw: Only fold in NSTable bit effects in Secure
From: |
Peter Maydell |
Subject: |
[PULL 20/35] target/arm/ptw: Only fold in NSTable bit effects in Secure state |
Date: |
Thu, 24 Aug 2023 10:28:21 +0100 |
When we do a translation in Secure state, the NSTable bits in table
descriptors may downgrade us to NonSecure; we update ptw->in_secure
and ptw->in_space accordingly. We guard that check correctly with a
conditional that means it's only applied for Secure stage 1
translations. However, later on in get_phys_addr_lpae() we fold the
effects of the NSTable bits into the final descriptor attributes
bits, and there we do it unconditionally regardless of the CPU state.
That means that in Realm state (where in_secure is false) we will set
bit 5 in attrs, and later use it to decide to output to non-secure
space.
We don't in fact need to do this folding in at all any more (since
commit 2f1ff4e7b9f30c): if an NSTable bit was set then we have
already set ptw->in_space to ARMSS_NonSecure, and in that situation
we don't look at attrs bit 5. The only thing we still need to deal
with is the real NS bit in the final descriptor word, so we can just
drop the code that ORed in the NSTable bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-9-peter.maydell@linaro.org
---
target/arm/ptw.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 4c60de753dd..6e736bacd77 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1886,11 +1886,10 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
* Extract attributes from the (modified) descriptor, and apply
* table descriptors. Stage 2 table descriptors do not include
* any attribute fields. HPD disables all the table attributes
- * except NSTable.
+ * except NSTable (which we have already handled).
*/
attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50,
14));
if (!regime_is_stage2(mmu_idx)) {
- attrs |= !ptw->in_secure << 5; /* NS */
if (!param.hpd) {
attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */
/*
--
2.34.1
- [PULL 22/35] target/arm/ptw: Remove S1Translate::in_secure, (continued)
- [PULL 22/35] target/arm/ptw: Remove S1Translate::in_secure, Peter Maydell, 2023/08/24
- [PULL 08/35] accel/kvm: Specify default IPA size for arm64, Peter Maydell, 2023/08/24
- [PULL 27/35] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types, Peter Maydell, 2023/08/24
- [PULL 31/35] target/arm: Pass security space rather than flag for AT instructions, Peter Maydell, 2023/08/24
- [PULL 12/35] accel/kvm: Make kvm_dirty_ring_reaper_init() void, Peter Maydell, 2023/08/24
- [PULL 34/35] target/arm: Fix SME ST1Q, Peter Maydell, 2023/08/24
- [PULL 33/35] target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK, Peter Maydell, 2023/08/24
- [PULL 18/35] target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate(), Peter Maydell, 2023/08/24
- [PULL 14/35] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults, Peter Maydell, 2023/08/24
- [PULL 21/35] target/arm/ptw: Remove last uses of ptw->in_secure, Peter Maydell, 2023/08/24
- [PULL 20/35] target/arm/ptw: Only fold in NSTable bit effects in Secure state,
Peter Maydell <=
- [PULL 29/35] target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2*, Peter Maydell, 2023/08/24
- Re: [PULL 00/35] target-arm queue, Stefan Hajnoczi, 2023/08/24