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[PULL 20/48] target/m68k: Use tcg_gen_negsetcond_*
From: |
Richard Henderson |
Subject: |
[PULL 20/48] target/m68k: Use tcg_gen_negsetcond_* |
Date: |
Wed, 23 Aug 2023 13:22:58 -0700 |
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d08e823b6c..15b3701b8f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1350,8 +1350,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
c->v1 = tmp = tcg_temp_new();
- tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
- tcg_gen_neg_i32(tmp, tmp);
+ tcg_gen_negsetcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tmp2 = tcg_temp_new();
tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
tcg_gen_or_i32(tmp, tmp, tmp2);
@@ -1430,9 +1429,8 @@ DISAS_INSN(scc)
gen_cc_cond(&c, s, cond);
tmp = tcg_temp_new();
- tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
+ tcg_gen_negsetcond_i32(c.tcond, tmp, c.v1, c.v2);
- tcg_gen_neg_i32(tmp, tmp);
DEST_EA(env, insn, OS_BYTE, tmp, NULL);
}
@@ -2764,13 +2762,14 @@ DISAS_INSN(mull)
tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
/* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
- tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
+ tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V,
+ QREG_CC_V, QREG_CC_Z);
} else {
tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
/* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
- tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
+ tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V,
+ QREG_CC_V, QREG_CC_C);
}
- tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
@@ -3339,14 +3338,13 @@ static inline void shift_im(DisasContext *s, uint16_t
insn, int opsize)
if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) {
/* if shift count >= bits, V is (reg != 0) */
if (count >= bits) {
- tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
+ tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
} else {
TCGv t0 = tcg_temp_new();
tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
tcg_gen_sari_i32(t0, reg, bits - count - 1);
- tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
+ tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
}
- tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
}
} else {
tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
@@ -3430,9 +3428,8 @@ static inline void shift_reg(DisasContext *s, uint16_t
insn, int opsize)
/* Ignore the bits below the sign bit. */
tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
/* If any bits remain set, we have overflow. */
- tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
+ tcg_gen_negsetcond_i64(TCG_COND_NE, t64, t64, tcg_constant_i64(0));
tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
- tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
}
} else {
tcg_gen_shli_i64(t64, t64, 32);
@@ -5311,9 +5308,8 @@ DISAS_INSN(fscc)
gen_fcc_cond(&c, s, cond);
tmp = tcg_temp_new();
- tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
+ tcg_gen_negsetcond_i32(c.tcond, tmp, c.v1, c.v2);
- tcg_gen_neg_i32(tmp, tmp);
DEST_EA(env, insn, OS_BYTE, tmp, NULL);
}
--
2.34.1
- [PULL 34/48] tcg/i386: Merge tcg_out_movcond{32,64}, (continued)
- [PULL 34/48] tcg/i386: Merge tcg_out_movcond{32,64}, Richard Henderson, 2023/08/23
- [PULL 39/48] tcg/tcg-op: Document bswap16_i32() byte pattern, Richard Henderson, 2023/08/23
- [PULL 06/48] include/exec: typedef abi_ptr to vaddr in softmmu, Richard Henderson, 2023/08/23
- [PULL 01/48] accel/kvm: Widen pc/saved_insn for kvm_sw_breakpoint, Richard Henderson, 2023/08/23
- [PULL 32/48] tcg/i386: Merge tcg_out_brcond{32,64}, Richard Henderson, 2023/08/23
- [PULL 27/48] tcg/aarch64: Implement negsetcond_*, Richard Henderson, 2023/08/23
- [PULL 24/48] target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl, Richard Henderson, 2023/08/23
- [PULL 31/48] tcg/sparc64: Implement negsetcond_*, Richard Henderson, 2023/08/23
- [PULL 33/48] tcg/i386: Merge tcg_out_setcond{32,64}, Richard Henderson, 2023/08/23
- [PULL 35/48] tcg/i386: Use CMP+SBB in tcg_out_setcond, Richard Henderson, 2023/08/23
- [PULL 20/48] target/m68k: Use tcg_gen_negsetcond_*,
Richard Henderson <=
- [PULL 19/48] target/arm: Use tcg_gen_negsetcond_*, Richard Henderson, 2023/08/23
- [PULL 37/48] tcg/i386: Use shift in tcg_out_setcond, Richard Henderson, 2023/08/23
- [PULL 36/48] tcg/i386: Clear dest first in tcg_out_setcond if possible, Richard Henderson, 2023/08/23
- [PULL 13/48] tcg/i386: Allow immediate as input to deposit_*, Richard Henderson, 2023/08/23
- [PULL 14/48] docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32(), Richard Henderson, 2023/08/23
- [PULL 07/48] include/exec: Widen tlb_hit/tlb_hit_page(), Richard Henderson, 2023/08/23
- [PULL 09/48] accel/tcg: Update run_on_cpu_data static assert, Richard Henderson, 2023/08/23
- [PULL 15/48] tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32, Richard Henderson, 2023/08/23
- [PULL 23/48] target/sparc: Use tcg_gen_movcond_i64 in gen_edge, Richard Henderson, 2023/08/23
- [PULL 26/48] tcg/ppc: Use the Set Boolean Extension, Richard Henderson, 2023/08/23