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[Stable-8.0.4 61/63] hw/i386/intel_iommu: Fix index calculation in vtd_i
From: |
Michael Tokarev |
Subject: |
[Stable-8.0.4 61/63] hw/i386/intel_iommu: Fix index calculation in vtd_interrupt_remap_msi() |
Date: |
Fri, 4 Aug 2023 22:16:44 +0300 |
From: Thomas Huth <thuth@redhat.com>
The values in "addr" are populated locally in this function in host
endian byte order, so we must not swap the index_l field here.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230802135723.178083-5-thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Xu <peterx@redhat.com>
(cherry picked from commit fcd8027423300b201b37842b88393dc5c6c8ee9e)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 03becd6384..9e6ce71454 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3458,7 +3458,7 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
goto out;
}
- index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
+ index = addr.addr.index_h << 15 | addr.addr.index_l;
#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
--
2.39.2
- [PATCH v5 0/8] Xilinx Versal CFI support, Francisco Iglesias, 2023/08/31
- [PATCH v5 1/8] hw/misc: Introduce the Xilinx CFI interface, Francisco Iglesias, 2023/08/31
- [PATCH v5 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO, Francisco Iglesias, 2023/08/31
- [PATCH v5 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG, Francisco Iglesias, 2023/08/31
- [PATCH v5 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG, Francisco Iglesias, 2023/08/31
- [PATCH v5 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR, Francisco Iglesias, 2023/08/31
- [PATCH v5 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB, Francisco Iglesias, 2023/08/31
- [PATCH v5 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR, Francisco Iglesias, 2023/08/31
- [PATCH v5 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG, Francisco Iglesias, 2023/08/31