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Re: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode CPUID[
From: |
Moger, Babu |
Subject: |
Re: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] |
Date: |
Thu, 3 Aug 2023 15:44:13 -0500 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 |
Hi Zhao,
Please copy the thread to kvm@vger.kernel.org also. It makes it easier
to browse.
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> CPUID[0x8000001D].EAX[bits 25:14] is used to represent the cache
> topology for amd CPUs.
Please change this to.
CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache. The number of
logical processors sharing this cache is NumSharingCache + 1.
>
> After cache models have topology information, we can use
> CPUCacheInfo.share_level to decide which topology level to be encoded
> into CPUID[0x8000001D].EAX[bits 25:14].
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> Changes since v1:
> * Use cache->share_level as the parameter in
> max_processor_ids_for_cache().
> ---
> target/i386/cpu.c | 10 +---------
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index f67b6be10b8d..6eee0274ade4 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -361,20 +361,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
> *cache,
> uint32_t *eax, uint32_t *ebx,
> uint32_t *ecx, uint32_t *edx)
> {
> - uint32_t num_apic_ids;
> assert(cache->size == cache->line_size * cache->associativity *
> cache->partitions * cache->sets);
>
> *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
> (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
> -
> - /* L3 is shared among multiple cores */
> - if (cache->level == 3) {
> - num_apic_ids = 1 << apicid_die_offset(topo_info);
> - } else {
> - num_apic_ids = 1 << apicid_core_offset(topo_info);
> - }
> - *eax |= (num_apic_ids - 1) << 14;
> + *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14;
>
> assert(cache->line_size > 0);
> assert(cache->partitions > 0);
--
Thanks
Babu Moger
- Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4], (continued)
- Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Moger, Babu, 2023/08/04
- Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2023/08/14
- Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Moger, Babu, 2023/08/14
- Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2023/08/18
- Re: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Moger, Babu, 2023/08/23
[PATCH v3 15/17] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/08/01
[PATCH v3 17/17] i386: Add new property to control L2 cache topo in CPUID.04H, Zhao Liu, 2023/08/01
[PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/08/01
- Re: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14],
Moger, Babu <=
Re: [PATCH v3 00/17] Support smp.clusters for x86, Jonathan Cameron, 2023/08/01
Re: [PATCH v3 00/17] Support smp.clusters for x86, Moger, Babu, 2023/08/01