Re: [PATCH v4 0/5] Support x2APIC mode with TCG accelerator

[Bui Quang Minh]

On 7/11/23 01:39, Michael S. Tsirkin wrote:
> On Mon, May 22, 2023 at 11:31:52PM +0700, Bui Quang Minh wrote:
> > Hi everyone,
> >
> > This series implements x2APIC mode in userspace local APIC and the
> > RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
> > and AMD iommu are adjusted to support x2APIC interrupt remapping. With this
> > series, we can now boot Linux kernel into x2APIC mode with TCG accelerator
> > using either Intel or AMD iommu.
> >
> > Testing to boot my own built Linux 6.3.0-rc2, the kernel successfully boot
> > with enabled x2APIC and can enumerate CPU with APIC ID 257
> >
> > Using Intel IOMMU
> >
> > qemu/build/qemu-system-x86_64 \
> >    -smp 2,maxcpus=260 \
> >    -cpu qemu64,x2apic=on \
> >    -machine q35 \
> >    -device intel-iommu,intremap=on,eim=on \
> >    -device qemu64-x86_64-cpu,x2apic=on,core-id=257,socket-id=0,thread-id=0 \
> >    -m 2G \
> >    -kernel $KERNEL_DIR \
> >    -append "nokaslr console=ttyS0 root=/dev/sda earlyprintk=serial 
> > net.ifnames=0" \
> >    -drive file=$IMAGE_DIR,format=raw \
> >    -nographic \
> >    -s
> >
> > Using AMD IOMMU
> >
> > qemu/build/qemu-system-x86_64 \
> >    -smp 2,maxcpus=260 \
> >    -cpu qemu64,x2apic=on \
> >    -machine q35 \
> >    -device amd-iommu,intremap=on,xtsup=on \
> >    -device qemu64-x86_64-cpu,x2apic=on,core-id=257,socket-id=0,thread-id=0 \
> >    -m 2G \
> >    -kernel $KERNEL_DIR \
> >    -append "nokaslr console=ttyS0 root=/dev/sda earlyprintk=serial 
> > net.ifnames=0" \
> >    -drive file=$IMAGE_DIR,format=raw \
> >    -nographic \
> >    -s
> >
> > Testing the emulated userspace APIC with kvm-unit-tests, disable test
> > device with this patch
> >
> > diff --git a/lib/x86/fwcfg.c b/lib/x86/fwcfg.c
> > index 1734afb..f56fe1c 100644
> > --- a/lib/x86/fwcfg.c
> > +++ b/lib/x86/fwcfg.c
> > @@ -27,6 +27,7 @@ static void read_cfg_override(void)
> >   
> >          if ((str = getenv("TEST_DEVICE")))
> >                  no_test_device = !atol(str);
> > +       no_test_device = true;
> >   
> >          if ((str = getenv("MEMLIMIT")))
> >                  fw_override[FW_CFG_MAX_RAM] = atol(str) * 1024 * 1024;
> >
> > ~ env QEMU=/home/minh/Desktop/oss/qemu/build/qemu-system-x86_64 ACCEL=tcg \
> > ./run_tests.sh -v -g apic
> >
> > TESTNAME=apic-split TIMEOUT=90s ACCEL=tcg ./x86/run x86/apic.flat -smp 2
> > -cpu qemu64,+x2apic,+tsc-deadline -machine kernel_irqchip=split FAIL
> > apic-split (54 tests, 8 unexpected failures, 1 skipped)
> > TESTNAME=ioapic-split TIMEOUT=90s ACCEL=tcg ./x86/run x86/ioapic.flat -smp
> > 1 -cpu qemu64 -machine kernel_irqchip=split PASS ioapic-split (19 tests)
> > TESTNAME=x2apic TIMEOUT=30 ACCEL=tcg ./x86/run x86/apic.flat -smp 2 -cpu
> > qemu64,+x2apic,+tsc-deadline FAIL x2apic (54 tests, 8 unexpected failures,
> > 1 skipped) TESTNAME=xapic TIMEOUT=60 ACCEL=tcg ./x86/run x86/apic.flat -smp
> > 2 -cpu qemu64,-x2apic,+tsc-deadline -machine pit=off FAIL xapic (43 tests,
> > 6 unexpected failures, 2 skipped)
> >
> >    FAIL: apic_disable: *0xfee00030: 50014
> >    FAIL: apic_disable: *0xfee00080: f0
> >    FAIL: apic_disable: *0xfee00030: 50014
> >    FAIL: apic_disable: *0xfee00080: f0
> >    FAIL: apicbase: relocate apic
> >
> > These errors are because we don't disable MMIO region when switching to
> > x2APIC and don't support relocate MMIO region yet. This is a problem
> > because, MMIO region is the same for all CPUs, in order to support these we
> > need to figure out how to allocate and manage different MMIO regions for
> > each CPUs. This can be an improvement in the future.
> >
> >    FAIL: nmi-after-sti
> >    FAIL: multiple nmi
> >
> > These errors are in the way we handle CPU_INTERRUPT_NMI in core TCG.
> >
> >    FAIL: TMCCT should stay at zero
> >
> > This error is related to APIC timer which should be addressed in separate
> > patch.
>
> So, I'm not sure how safe it is to merge as is - are we
> creating a way for users to shoot themselves in the foot?
> Would be better to just fix these issues before we merge.

I may be biased as I am the author and willing this to be merged. These 
issues are not created by this series, the current APIC implementation 
fails those tests too.

Currently, I only have some ideas to fix the timer failed test case. The 
timer failed test case is that when the timer is in one-shot mode, the 
initial count is non-zero. If the current count reaches 0, a timer 
interrupt is delivered and no more interrupt. At this time, if we write 
to timer LVT to change to periodic mode, according to Intel SDM Section 
11.5.4 APIC timer

"Changing the mode of the APIC timer (from one-shot to periodic or vice 
versa) by writing to the
timer LVT entry does not start the timer. To start the timer, it is 
necessary to write to the initial-
count register as described above"

So it is expected that periodic mode does not start until initial count 
is written. However, in our current implementation, we see the initial 
is non-zero, so we start the new periodic timer. The solution might be 
not calling apic_timer_update when timer LVT written anymore and make 
the apic_get_current_count returns 0 in the above case.

In my opinion, this series is expected to add the x2APIC feature, so if 
the user wants to use it, they need to enable this CPU feature flag. 
Otherwise, with their old configuration, it is expected to behave the same.

> > Version 4 changes,
> > - Patch 5:
> >    + Instead of replacing IVHD type 0x10 with type 0x11, export both types
> >    for backward compatibility with old guest operating system
> >    + Flip the xtsup feature check condition in amdvi_int_remap_ga for
> >    readability
> >
> > Version 3 changes,
> > - Patch 2:
> >    + Allow APIC ID > 255 only when x2APIC feature is supported on CPU
> >    + Make physical destination mode IPI which has destination id 0xffffffff
> >    a broadcast to xAPIC CPUs
> >    + Make cluster address 0xf in cluster model of xAPIC logical destination
> >    mode a broadcast to all clusters
> >    + Create new extended_log_dest to store APIC_LDR information in x2APIC
> >    instead of extending log_dest for backward compatibility in vmstate
> >
> > Version 2 changes,
> > - Add support for APIC ID larger than 255
> > - Adjust AMD iommu for x2APIC suuport
> > - Reorganize and split patch 1,2 into patch 1,2,3 in version 2
> >
> > Thanks,
> > Quang Minh.
> >
> > Bui Quang Minh (5):
> >    i386/tcg: implement x2APIC registers MSR access
> >    apic: add support for x2APIC mode
> >    apic, i386/tcg: add x2apic transitions
> >    intel_iommu: allow Extended Interrupt Mode when using userspace APIC
> >    amd_iommu: report x2APIC support to the operating system
> >
> >   hw/i386/acpi-build.c                 | 127 +++++----
> >   hw/i386/amd_iommu.c                  |  21 +-
> >   hw/i386/amd_iommu.h                  |  16 +-
> >   hw/i386/intel_iommu.c                |  11 -
> >   hw/i386/x86.c                        |   8 +-
> >   hw/intc/apic.c                       | 395 +++++++++++++++++++++------
> >   hw/intc/apic_common.c                |  16 +-
> >   hw/intc/trace-events                 |   4 +-
> >   include/hw/i386/apic.h               |   6 +-
> >   include/hw/i386/apic_internal.h      |   7 +-
> >   target/i386/cpu-sysemu.c             |  18 +-
> >   target/i386/cpu.c                    |   5 +-
> >   target/i386/cpu.h                    |   9 +
> >   target/i386/tcg/sysemu/misc_helper.c |  31 +++
> >   14 files changed, 500 insertions(+), 174 deletions(-)
> >
> > --
> > 2.25.1