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[PULL 27/44] target/mips/mxu: Add D32SARL D32SARW instructions
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 27/44] target/mips/mxu: Add D32SARL D32SARW instructions |
Date: |
Tue, 11 Jul 2023 00:25:54 +0200 |
From: Siarhei Volkau <lis8215@gmail.com>
These instructions are dual 32-bit arithmetic shift right and
pack LSBs to 2x 16-bit into a MXU register.
The difference is the shift amount source: immediate or GP reg.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-25-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/mxu_translate.c | 59 +++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 4f07201fcc..36fb4232cd 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -394,6 +394,7 @@ enum {
OPC_MXU_S16SDI = 0x2D,
OPC_MXU_S32M2I = 0x2E,
OPC_MXU_S32I2M = 0x2F,
+ OPC_MXU_D32SARL = 0x32,
OPC_MXU__POOL19 = 0x38,
};
@@ -492,6 +493,7 @@ enum {
* MXU pool 16
*/
enum {
+ OPC_MXU_D32SARW = 0x00,
OPC_MXU_S32ALN = 0x01,
OPC_MXU_S32ALNI = 0x02,
OPC_MXU_S32LUI = 0x03,
@@ -1689,6 +1691,57 @@ static void gen_mxu_S32XOR(DisasContext *ctx)
}
}
+/*
+ * MXU instruction category: shift
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * D32SLL D32SLR D32SAR D32SARL
+ * D32SLLV D32SLRV D32SARV D32SARW
+ * Q16SLL Q16SLR Q16SAR
+ * Q16SLLV Q16SLRV Q16SARV
+ */
+
+/*
+ * D32SARL XRa, XRb, XRc, SFT4
+ * Dual shift arithmetic right 32-bit integers in XRb and XRc
+ * to SFT4 bits (0..15). Pack 16 LSBs of each into XRa.
+ *
+ * D32SARW XRa, XRb, XRc, rb
+ * Dual shift arithmetic right 32-bit integers in XRb and XRc
+ * to rb[3:0] bits. Pack 16 LSBs of each into XRa.
+ */
+static void gen_mxu_d32sarl(DisasContext *ctx, bool sarw)
+{
+ uint32_t XRa, XRb, XRc, rb;
+
+ XRa = extract32(ctx->opcode, 6, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRc = extract32(ctx->opcode, 14, 4);
+ rb = extract32(ctx->opcode, 21, 5);
+
+ if (unlikely(XRa == 0)) {
+ /* destination is zero register -> do nothing */
+ } else {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ if (!sarw) {
+ /* Make SFT4 from rb field */
+ tcg_gen_movi_tl(t2, rb >> 1);
+ } else {
+ gen_load_gpr(t2, rb);
+ tcg_gen_andi_tl(t2, t2, 0x0f);
+ }
+ gen_load_mxu_gpr(t0, XRb);
+ gen_load_mxu_gpr(t1, XRc);
+ tcg_gen_sar_tl(t0, t0, t2);
+ tcg_gen_sar_tl(t1, t1, t2);
+ tcg_gen_extract_tl(t2, t1, 0, 16);
+ tcg_gen_deposit_tl(t2, t2, t0, 16, 16);
+ gen_store_mxu_gpr(t2, XRa);
+ }
+}
/*
* MXU instruction category max/min/avg
@@ -4003,6 +4056,9 @@ static void decode_opc_mxu__pool16(DisasContext *ctx)
uint32_t opcode = extract32(ctx->opcode, 18, 3);
switch (opcode) {
+ case OPC_MXU_D32SARW:
+ gen_mxu_d32sarl(ctx, true);
+ break;
case OPC_MXU_S32ALN:
gen_mxu_S32ALN(ctx);
break;
@@ -4214,6 +4270,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
case OPC_MXU_S16SDI:
gen_mxu_s16std(ctx, true);
break;
+ case OPC_MXU_D32SARL:
+ gen_mxu_d32sarl(ctx, false);
+ break;
case OPC_MXU__POOL19:
decode_opc_mxu__pool19(ctx);
break;
--
2.38.1
- [PULL 17/44] target/mips/mxu: Add Q16ADD instruction, (continued)
- [PULL 17/44] target/mips/mxu: Add Q16ADD instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 18/44] target/mips/mxu: Add D32ADD instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 19/44] target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 20/44] target/mips/mxu: Add D32ADDC instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 22/44] target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 23/44] target/mips/mxu: Add S8STD S8LDI S8SDI instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 21/44] target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 24/44] target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 25/44] target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 26/44] target/mips/mxu: Add S32ALN S32LUI insns, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 27/44] target/mips/mxu: Add D32SARL D32SARW instructions,
Philippe Mathieu-Daudé <=
- [PULL 28/44] target/mips/mxu: Add D32SLL D32SLR D32SAR instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 29/44] target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 30/44] target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 31/44] target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 32/44] target/mips/mxu: Add Q8MAC Q8MACSU instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 33/44] target/mips/mxu: Add Q16SCOP instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 34/44] target/mips/mxu: Add Q8MADL instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 35/44] target/mips/mxu: Add S32SFL instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 36/44] target/mips/mxu: Add Q8SAD instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 37/44] target/mips: enable GINVx support for I6400 and I6500, Philippe Mathieu-Daudé, 2023/07/10