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[PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
From: |
Peter Maydell |
Subject: |
[PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG |
Date: |
Thu, 6 Jul 2023 14:25:07 +0100 |
From: Fabiano Rosas <farosas@suse.de>
This code is only relevant when TCG is present in the build. Building
with --disable-tcg --enable-xen on an x86 host we get:
$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg
--enable-xen
$ make -j$(nproc)
...
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr':
../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr'
../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr'
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function
`arm_gdb_get_m_systemreg':
../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control'
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230628164821.16771-1-farosas@suse.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/gdbstub.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 03b17c814f6..f421c5d041c 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -324,6 +324,7 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int
base_reg)
return cpu->dyn_sysreg_xml.num;
}
+#ifdef CONFIG_TCG
typedef enum {
M_SYSREG_MSP,
M_SYSREG_PSP,
@@ -481,6 +482,7 @@ static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs,
int orig_base_reg)
return cpu->dyn_m_secextreg_xml.num;
}
#endif
+#endif /* CONFIG_TCG */
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
{
@@ -561,6 +563,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
"system-registers.xml", 0);
+#ifdef CONFIG_TCG
if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
gdb_register_coprocessor(cs,
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
@@ -575,4 +578,5 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
}
#endif
}
+#endif /* CONFIG_TCG */
}
--
2.34.1
- [PULL v2 00/14] target-arm queue, Peter Maydell, 2023/07/06
- [PULL 02/14] hw/arm/sbsa-ref: use XHCI to replace EHCI, Peter Maydell, 2023/07/06
- [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance, Peter Maydell, 2023/07/06
- [PULL 08/14] tests/qtest: xlnx-canfd-test: Fix code coverity issues, Peter Maydell, 2023/07/06
- [PULL 13/14] target/arm: Define neoverse-v1, Peter Maydell, 2023/07/06
- [PULL 06/14] target/arm: Fix SME full tile indexing, Peter Maydell, 2023/07/06
- [PULL 10/14] hw: arm: allwinner-sramc: Set class_size, Peter Maydell, 2023/07/06
- [PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG,
Peter Maydell <=
- [PULL 12/14] target/arm: Suppress more TCG unimplemented features in ID registers, Peter Maydell, 2023/07/06
- [PULL 05/14] target/arm: Dump ZA[] when active, Peter Maydell, 2023/07/06
- [PULL 07/14] target/arm: Handle IC IVAU to improve compatibility with JITs, Peter Maydell, 2023/07/06
- [PULL 03/14] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1, Peter Maydell, 2023/07/06
- [PULL 11/14] target/xtensa: Assert that interrupt level is within bounds, Peter Maydell, 2023/07/06
- [PULL 04/14] target/arm: Avoid splitting Zregs across lines in dump, Peter Maydell, 2023/07/06
- [PULL 14/14] target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case, Peter Maydell, 2023/07/06
- Re: [PULL v2 00/14] target-arm queue, Richard Henderson, 2023/07/06