Re: Emulation of 'System OFF' mode in ARM nRF51 SoCs

[Peter Maydell]

On Sat, 1 Jul 2023 at 20:29, Chris Laplante <chris@laplante.io> wrote:
>
> Hi Peter,
>
> > The reference manual is very unclear about what this "emulated
> > system off" mode actually does. I think that implementing
> > real "system off" is probably simpler. For that you should be able
> > to implement it something like this:
> >
> > (1) the power management device implements the SYSTEMOFF register
> > to call arm_set_cpu_off() when a 1 is written
> > (2) make sure the GPIO device implements DETECT as a GPIO output
> > signal, ie an outbound qemu_irq (if we don't do this already
> > the functionality will need to be added to the device model)
>
> Working on adding this now. One question - if the CPU is off (via 
> arm_set_cpu_off), will the 'DETECT' IRQ I add to nrf51_gpio.c still fire?

Yes. The only thing that turning the CPU off affects is
the CPU -- all the rest of the devices in the system
continue to behave as normal.

> > (3) similarly for ANADETECT from the LPCOMP device
> > (4) Wire those qemu_irq GPIO outputs up to inputs on the
> > power management device. When the power management device
> > sees those signals go high and the CPU is in system off mode,
> > it should trigger the reset of the CPU by calling
> > arm_set_cpu_on_and_reset().
> >
>
> There is no power management IC or device in this system.

The manual says there is: chapter 12 describes the
power management and the registers involved, which are
in the POWER peripheral part of the SoC, starting at
0x4000_0000. QEMU just doesn't model that yet.

thanks
-- PMM