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[PULL v2 33/44] Hexagon (target/hexagon/*.py): raise exception on reg pa
From: |
Taylor Simpson |
Subject: |
[PULL v2 33/44] Hexagon (target/hexagon/*.py): raise exception on reg parsing error |
Date: |
Thu, 18 May 2023 13:04:00 -0700 |
From: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a register. Let's
make the compilation properly fail in such cases by rasing an exception
instead of just printing a warning message, which might get lost in the
output.
This patch was generated with:
git grep -l "Bad register" *hexagon* | \
xargs sed -i "" -e 's/print("Bad register parse: "[,
]*\([^)]*\))/hex_common.bad_register(\1)/g'
Plus the bad_register() helper added to hex_common.py.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<1f5dbd92f68fdd89e2647e4ba527a2c32cf0f070.1683217043.git.quic_mathbern@quicinc.com>
---
target/hexagon/gen_analyze_funcs.py | 30 +++++-----
target/hexagon/gen_helper_funcs.py | 14 ++---
target/hexagon/gen_helper_protos.py | 2 +-
target/hexagon/gen_idef_parser_funcs.py | 2 +-
target/hexagon/gen_tcg_funcs.py | 78 ++++++++++++-------------
target/hexagon/hex_common.py | 3 +
6 files changed, 66 insertions(+), 63 deletions(-)
diff --git a/target/hexagon/gen_analyze_funcs.py
b/target/hexagon/gen_analyze_funcs.py
index d040f67001..00868cc6cb 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -47,7 +47,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid in {"s", "t", "u", "v"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
@@ -56,7 +56,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_pred_write(ctx, {regN});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "C":
if regid == "ss":
f.write(
@@ -77,13 +77,13 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
f.write(f" const int {regN} = insn->regno[{regno}] " "+
HEX_REG_SA0;\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "M":
if regid == "u":
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "V":
newv = "EXT_DFL"
if hex_common.is_new_result(tag):
@@ -105,7 +105,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, "
f"{predicated});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "Q":
if regid in {"d", "e", "x"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
@@ -114,7 +114,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_qreg_read(ctx, {regN});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "G":
if regid in {"dd"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
@@ -125,7 +125,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
elif regid in {"s"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "S":
if regid in {"dd"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
@@ -136,9 +136,9 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
elif regid in {"s"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def analyze_opn_new(f, tag, regtype, regid, regno):
@@ -148,21 +148,21 @@ def analyze_opn_new(f, tag, regtype, regid, regno):
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid in {"t", "u", "v"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_pred_read(ctx, {regN});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "O":
if regid == "s":
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_read(ctx, {regN});\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
@@ -174,9 +174,9 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
elif hex_common.is_new_val(regtype, regid, tag):
analyze_opn_new(f, tag, regtype, regid, i)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
##
diff --git a/target/hexagon/gen_helper_funcs.py
b/target/hexagon/gen_helper_funcs.py
index 39751a483c..e80550f94e 100755
--- a/target/hexagon/gen_helper_funcs.py
+++ b/target/hexagon/gen_helper_funcs.py
@@ -87,9 +87,9 @@ def gen_helper_arg_opn(f, regtype, regid, i, tag):
elif hex_common.is_new_val(regtype, regid, tag):
gen_helper_arg_new(f, regtype, regid, i)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
def gen_helper_arg_imm(f, immlett):
@@ -135,7 +135,7 @@ def gen_helper_dest_decl_opn(f, regtype, regid, i):
else:
gen_helper_dest_decl(f, regtype, regid, i)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
def gen_helper_src_var_ext(f, regtype, regid):
@@ -185,7 +185,7 @@ def gen_helper_return_opn(f, regtype, regid, i):
else:
gen_helper_return(f, regtype, regid, i)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
##
@@ -239,7 +239,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):
else:
gen_helper_return_type(f, regtype, regid, i)
else:
- print("Bad register parse: ", regtype, regid, toss,
numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
i += 1
if numscalarresults == 0:
@@ -262,7 +262,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):
# This is the return value of the function
continue
else:
- print("Bad register parse: ", regtype, regid, toss,
numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
i += 1
## For conditional instructions, we pass in the destination register
@@ -329,7 +329,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):
if hex_common.is_hvx_reg(regtype):
gen_helper_src_var_ext(f, regtype, regid)
else:
- print("Bad register parse: ", regtype, regid, toss,
numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
if hex_common.need_slot(tag):
if "A_LOAD" in hex_common.attribdict[tag]:
diff --git a/target/hexagon/gen_helper_protos.py
b/target/hexagon/gen_helper_protos.py
index c5ecb85294..3dedd76cb4 100755
--- a/target/hexagon/gen_helper_protos.py
+++ b/target/hexagon/gen_helper_protos.py
@@ -52,7 +52,7 @@ def gen_def_helper_opn(f, tag, regtype, regid, toss, numregs,
i):
elif hex_common.is_single(regid):
f.write(f", {def_helper_types[regtype]}")
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
##
diff --git a/target/hexagon/gen_idef_parser_funcs.py
b/target/hexagon/gen_idef_parser_funcs.py
index 639458b462..29160fcb1d 100644
--- a/target/hexagon/gen_idef_parser_funcs.py
+++ b/target/hexagon/gen_idef_parser_funcs.py
@@ -147,7 +147,7 @@ def main():
elif is_single_new:
arguments.append(f"{prefix}{regtype}{regid}N")
else:
- print("Bad register parse: ", regtype, regid, toss,
numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
for immlett, bits, immshift in imms:
arguments.append(hex_common.imm_name(immlett))
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index 887b1cd369..c73467b840 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -37,7 +37,7 @@ def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
elif regtype == "C":
f.write(f" const int {regN} = insn->regno[{regno}] +
HEX_REG_SA0;\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
f.write(f" TCGv_i64 {regtype}{regid}V = " f"get_result_gpr_pair(ctx,
{regN});\n")
@@ -53,7 +53,7 @@ def genptr_decl_writable(f, tag, regtype, regid, regno):
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" TCGv {regtype}{regid}V = tcg_temp_new();\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def genptr_decl(f, tag, regtype, regid, regno):
@@ -71,7 +71,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
elif regid in {"d", "e", "x", "y"}:
genptr_decl_writable(f, tag, regtype, regid, regno)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid in {"s", "t", "u", "v"}:
f.write(
@@ -80,7 +80,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
elif regid in {"d", "e", "x"}:
genptr_decl_writable(f, tag, regtype, regid, regno)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "C":
if regid == "ss":
f.write(f" TCGv_i64 {regtype}{regid}V = "
f"tcg_temp_new_i64();\n")
@@ -96,7 +96,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
elif regid == "d":
genptr_decl_writable(f, tag, regtype, regid, regno)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "M":
if regid == "u":
f.write(f" const int {regtype}{regid}N = "
f"insn->regno[{regno}];\n")
@@ -105,7 +105,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
"HEX_REG_M0];\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "V":
if regid in {"dd"}:
f.write(f" const int {regtype}{regid}N = "
f"insn->regno[{regno}];\n")
@@ -159,7 +159,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
f"{regtype}{regid}V_off);\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "Q":
if regid in {"d", "e", "x"}:
f.write(f" const int {regtype}{regid}N = "
f"insn->regno[{regno}];\n")
@@ -180,9 +180,9 @@ def genptr_decl(f, tag, regtype, regid, regno):
if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = "
"tcg_temp_new_ptr();\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def genptr_decl_new(f, tag, regtype, regid, regno):
@@ -193,7 +193,7 @@ def genptr_decl_new(f, tag, regtype, regid, regno):
f"get_result_gpr(ctx, insn->regno[{regno}]);\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid in {"t", "u", "v"}:
f.write(
@@ -201,7 +201,7 @@ def genptr_decl_new(f, tag, regtype, regid, regno):
f"ctx->new_pred_value[insn->regno[{regno}]];\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "O":
if regid == "s":
f.write(
@@ -218,9 +218,9 @@ def genptr_decl_new(f, tag, regtype, regid, regno):
f"tcg_constant_tl({regtype}{regid}N_num);\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def genptr_decl_opn(f, tag, regtype, regid, toss, numregs, i):
@@ -232,9 +232,9 @@ def genptr_decl_opn(f, tag, regtype, regid, toss, numregs,
i):
elif hex_common.is_new_val(regtype, regid, tag):
genptr_decl_new(f, tag, regtype, regid, i)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
def genptr_decl_imm(f, immlett):
@@ -266,7 +266,7 @@ def genptr_src_read(f, tag, regtype, regid):
f"hex_gpr[{regtype}{regid}N]);\n"
)
elif regid not in {"s", "t", "u", "v"}:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid == "x":
f.write(
@@ -274,7 +274,7 @@ def genptr_src_read(f, tag, regtype, regid):
f"hex_pred[{regtype}{regid}N]);\n"
)
elif regid not in {"s", "t", "u", "v"}:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "C":
if regid == "ss":
f.write(
@@ -287,10 +287,10 @@ def genptr_src_read(f, tag, regtype, regid):
f"{regtype}{regid}V);\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "M":
if regid != "u":
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "V":
if regid in {"uu", "vv", "xx"}:
f.write(f" tcg_gen_gvec_mov(MO_64, {regtype}{regid}V_off,\n")
@@ -311,7 +311,7 @@ def genptr_src_read(f, tag, regtype, regid):
f.write(f" vreg_src_off(ctx, {regtype}{regid}N),\n")
f.write(" sizeof(MMVector), sizeof(MMVector));\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "Q":
if regid in {"s", "t", "u", "v"}:
if not hex_common.skip_qemu_helper(tag):
@@ -326,23 +326,23 @@ def genptr_src_read(f, tag, regtype, regid):
)
f.write(" sizeof(MMQReg), sizeof(MMQReg));\n")
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def genptr_src_read_new(f, regtype, regid):
if regtype == "N":
if regid not in {"s", "t"}:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid not in {"t", "u", "v"}:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "O":
if regid != "s":
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def genptr_src_read_opn(f, regtype, regid, tag):
@@ -354,9 +354,9 @@ def genptr_src_read_opn(f, regtype, regid, tag):
elif hex_common.is_new_val(regtype, regid, tag):
genptr_src_read_new(f, regtype, regid)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
def gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i):
@@ -370,9 +370,9 @@ def gen_helper_call_opn(f, tag, regtype, regid, toss,
numregs, i):
elif hex_common.is_new_val(regtype, regid, tag):
f.write(f"{regtype}{regid}N")
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
def gen_helper_decl_imm(f, immlett):
@@ -401,7 +401,7 @@ def genptr_dst_write(f, tag, regtype, regid):
f"{regtype}{regid}V);\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid in {"d", "e", "x"}:
f.write(
@@ -409,7 +409,7 @@ def genptr_dst_write(f, tag, regtype, regid):
f"{regtype}{regid}V);\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "C":
if regid == "dd":
f.write(
@@ -422,9 +422,9 @@ def genptr_dst_write(f, tag, regtype, regid):
f"{regtype}{regid}V);\n"
)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
@@ -440,12 +440,12 @@ def genptr_dst_write_ext(f, tag, regtype, regid,
newv="EXT_DFL"):
f"{regtype}{regid}N, {newv});\n"
)
elif regid not in {"dd", "d", "x"}:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
elif regtype == "Q":
if regid not in {"d", "e", "x"}:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
else:
- print("Bad register parse: ", regtype, regid)
+ hex_common.bad_register(regtype, regid)
def genptr_dst_write_opn(f, regtype, regid, tag):
@@ -468,7 +468,7 @@ def genptr_dst_write_opn(f, regtype, regid, tag):
else:
genptr_dst_write(f, tag, regtype, regid)
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
##
@@ -532,7 +532,7 @@ def gen_tcg_func(f, tag, regs, imms):
elif hex_common.is_new_val(regtype, regid, tag):
declared.append(f"{regtype}{regid}N")
else:
- print("Bad register parse: ", regtype, regid, toss, numregs)
+ hex_common.bad_register(regtype, regid, toss, numregs)
## Handle immediates
for immlett, bits, immshift in imms:
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 011cce1a68..f3aac55db0 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -30,6 +30,9 @@
overrides = {} # tags with helper overrides
idef_parser_enabled = {} # tags enabled for idef-parser
+def bad_register(*args):
+ args_str = ", ".join(map(str, args))
+ raise Exception(f"Bad register parse: {args_str}")
# We should do this as a hash for performance,
# but to keep order let's keep it as a list.
--
2.25.1
- [PULL v2 23/44] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets, (continued)
- [PULL v2 23/44] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets, Taylor Simpson, 2023/05/18
- [PULL v2 21/44] Hexagon (target/hexagon) Short-circuit packet predicate writes, Taylor Simpson, 2023/05/18
- [PULL v2 18/44] Hexagon (target/hexagon) Don't overlap dest writes with source reads, Taylor Simpson, 2023/05/18
- [PULL v2 25/44] Hexagon (target/hexagon) Make special new_value for USR, Taylor Simpson, 2023/05/18
- [PULL v2 10/44] meson.build Add CONFIG_HEXAGON_IDEF_PARSER, Taylor Simpson, 2023/05/18
- [PULL v2 35/44] Hexagon: append eflags to unknown cpu model string, Taylor Simpson, 2023/05/18
- [PULL v2 08/44] Hexagon (target/hexagon) Add v73 scalar instructions, Taylor Simpson, 2023/05/18
- [PULL v2 30/44] Hexagon (target/hexagon) Move items to DisasContext, Taylor Simpson, 2023/05/18
- [PULL v2 31/44] Hexagon (target/hexagon) Additional instructions handled by idef-parser, Taylor Simpson, 2023/05/18
- [PULL v2 27/44] Hexagon (target/hexagon) Move new_pred_value to DisasContext, Taylor Simpson, 2023/05/18
- [PULL v2 33/44] Hexagon (target/hexagon/*.py): raise exception on reg parsing error,
Taylor Simpson <=
- [PULL v2 28/44] Hexagon (target/hexagon) Move pred_written to DisasContext, Taylor Simpson, 2023/05/18
- [PULL v2 04/44] Hexagon (target/hexagon) Add v68 HVX instructions, Taylor Simpson, 2023/05/18
- [PULL v2 36/44] Hexagon (iclass): update J4_hintjumpr slot constraints, Taylor Simpson, 2023/05/18
- [PULL v2 29/44] Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext, Taylor Simpson, 2023/05/18
- [PULL v2 19/44] Hexagon (target/hexagon) Mark registers as read during packet analysis, Taylor Simpson, 2023/05/18
- [PULL v2 40/44] gdbstub: add test for untimely stop-reply packets, Taylor Simpson, 2023/05/18
- [PULL v2 41/44] Hexagon: add core gdbstub xml data for LLDB, Taylor Simpson, 2023/05/18
- [PULL v2 43/44] Hexagon (gdbstub): add HVX support, Taylor Simpson, 2023/05/18
- [PULL v2 42/44] Hexagon (gdbstub): fix p3:0 read and write via stub, Taylor Simpson, 2023/05/18
- [PULL v2 44/44] Hexagon (linux-user/hexagon): handle breakpoints, Taylor Simpson, 2023/05/18