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[PULL 11/89] target/riscv: add support for Zcf extension
From: |
Alistair Francis |
Subject: |
[PULL 11/89] target/riscv: add support for Zcf extension |
Date: |
Fri, 5 May 2023 11:01:23 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16.decode | 8 ++++----
target/riscv/insn_trans/trans_rvf.c.inc | 18 ++++++++++++++++++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index ccfe59f294..f3ea650325 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -109,11 +109,11 @@ sw 110 ... ... .. ... 00 @cs_w
# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
{
ld 011 ... ... .. ... 00 @cl_d
- flw 011 ... ... .. ... 00 @cl_w
+ c_flw 011 ... ... .. ... 00 @cl_w
}
{
sd 111 ... ... .. ... 00 @cs_d
- fsw 111 ... ... .. ... 00 @cs_w
+ c_fsw 111 ... ... .. ... 00 @cs_w
}
# *** RV32/64C Standard Extension (Quadrant 1) ***
@@ -174,9 +174,9 @@ sw 110 . ..... ..... 10 @c_swsp
{
c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
ld 011 . ..... ..... 10 @c_ldsp
- flw 011 . ..... ..... 10 @c_lwsp
+ c_flw 011 . ..... ..... 10 @c_lwsp
}
{
sd 111 . ..... ..... 10 @c_sdsp
- fsw 111 . ..... ..... 10 @c_swsp
+ c_fsw 111 . ..... ..... 10 @c_swsp
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index 052408f45c..9e9fa2087a 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -30,6 +30,12 @@
} \
} while (0)
+#define REQUIRE_ZCF(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcf) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGv_i64 dest;
@@ -61,6 +67,18 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
return true;
}
+static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
+{
+ REQUIRE_ZCF(ctx);
+ return trans_flw(ctx, a);
+}
+
+static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
+{
+ REQUIRE_ZCF(ctx);
+ return trans_fsw(ctx, a);
+}
+
static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
{
REQUIRE_FPU;
--
2.40.0
- [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig, (continued)
- [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig, Alistair Francis, 2023/05/04
- [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh, Alistair Francis, 2023/05/04
- [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env, Alistair Francis, 2023/05/04
- [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState, Alistair Francis, 2023/05/04
- [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check, Alistair Francis, 2023/05/04
- [PULL 06/89] target/riscv: refactor Zicond support, Alistair Francis, 2023/05/04
- [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions, Alistair Francis, 2023/05/04
- [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry, Alistair Francis, 2023/05/04
- [PULL 09/89] target/riscv: add cfg properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 10/89] target/riscv: add support for Zca extension, Alistair Francis, 2023/05/04
- [PULL 11/89] target/riscv: add support for Zcf extension,
Alistair Francis <=
- [PULL 12/89] target/riscv: add support for Zcd extension, Alistair Francis, 2023/05/04
- [PULL 13/89] target/riscv: add support for Zcb extension, Alistair Francis, 2023/05/04
- [PULL 14/89] target/riscv: add support for Zcmp extension, Alistair Francis, 2023/05/04
- [PULL 15/89] target/riscv: add support for Zcmt extension, Alistair Francis, 2023/05/04
- [PULL 16/89] target/riscv: expose properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 17/89] disas/riscv.c: add disasm support for Zc*, Alistair Francis, 2023/05/04
- [PULL 18/89] target/riscv: Add support for Zce, Alistair Francis, 2023/05/04
- [PULL 19/89] target/riscv: Fix itrigger when icount is used, Alistair Francis, 2023/05/04