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Re: [PATCH v3 7/8] target/i386/intel-pt: Define specific PT feature set
From: |
Chenyi Qiang |
Subject: |
Re: [PATCH v3 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge |
Date: |
Fri, 9 Dec 2022 15:11:35 +0800 |
User-agent: |
Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.5.1 |
On 12/8/2022 2:25 PM, Xiaoyao Li wrote:
> For IceLake-server, it's just the same as using the default PT
> feature set since the default one is exact taken from ICX.
>
> For Snowridge, define it according to real SNR silicon capabilities.
>
> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> target/i386/cpu.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 24f3c7b06698..ef574c819671 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3458,6 +3458,14 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_6_EAX] =
> CPUID_6_EAX_ARAT,
> /* Missing: Mode-based execute control (XS/XU), processor tracing,
> TSC scaling */
> + .features[FEAT_14_0_EBX] =
> + CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB |
> + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC,
> + .features[FEAT_14_0_ECX] =
> + CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES |
> + CPUID_14_0_ECX_SINGLE_RANGE,
> + .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2,
> + .features[FEAT_14_1_EBX] = 0x003f << 16 | 0x1fff,
> .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
> MSR_VMX_BASIC_TRUE_CTLS,
> .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
> @@ -3735,6 +3743,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> CPUID_XSAVE_XGETBV1,
> .features[FEAT_6_EAX] =
> CPUID_6_EAX_ARAT,
> + .features[FEAT_14_0_EBX] =
> + CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB |
> + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC |
> + CPUID_14_0_EBX_PTWRITE | CPUID_14_0_EBX_POWER_EVENT |
> + CPUID_14_0_EBX_PSB_PMI_PRESERVATION,
> + .features[FEAT_14_0_ECX] =
> + CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES |
> + CPUID_14_0_ECX_SINGLE_RANGE | CPUID_14_0_ECX_LIP,
> + .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2,
> + .features[FEAT_14_1_EBX] = 0x003f << 16 | 0xffff,
> .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
> MSR_VMX_BASIC_TRUE_CTLS,
> .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
Is it acceptable to add the whole FEATURE_WORDS in the default version
of CPU model, or need to put in the versioned one (e.g. Snowridge-v5)?
- [PATCH v3 0/8] Make Intel PT configurable, Xiaoyao Li, 2022/12/08
- [PATCH v3 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge, Xiaoyao Li, 2022/12/08
- Re: [PATCH v3 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge,
Chenyi Qiang <=
- [PATCH v3 8/8] target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration, Xiaoyao Li, 2022/12/08
- [PATCH v3 5/8] target/i386/intel-pt: Rework/rename the default INTEL-PT feature set, Xiaoyao Li, 2022/12/08
- [PATCH v3 2/8] target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK, Xiaoyao Li, 2022/12/08
- [PATCH v3 6/8] target/i386/intel-pt: Enable host pass through of Intel PT, Xiaoyao Li, 2022/12/08