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[PULL 20/24] target/arm: Change gen_jmp* to work on displacements
From: |
Peter Maydell |
Subject: |
[PULL 20/24] target/arm: Change gen_jmp* to work on displacements |
Date: |
Thu, 20 Oct 2022 13:21:42 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 37 +++++++++++++++++++++----------------
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9104ab82325..ca128edab7e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -266,6 +266,12 @@ static uint32_t read_pc(DisasContext *s)
return s->pc_curr + (s->thumb ? 4 : 8);
}
+/* The pc_curr difference for an architectural jump. */
+static target_long jmp_diff(DisasContext *s, target_long diff)
+{
+ return diff + (s->thumb ? 4 : 8);
+}
+
/* Set a variable to the value of a CPU register. */
void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
{
@@ -2592,7 +2598,7 @@ static void gen_goto_ptr(void)
* cpu_loop_exec. Any live exit_requests will be processed as we
* enter the next TB.
*/
-static void gen_goto_tb(DisasContext *s, int n, int diff)
+static void gen_goto_tb(DisasContext *s, int n, target_long diff)
{
target_ulong dest = s->pc_curr + diff;
@@ -2608,10 +2614,8 @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
}
/* Jump, specifying which TB number to use if we gen_goto_tb() */
-static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
+static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno)
{
- int diff = dest - s->pc_curr;
-
if (unlikely(s->ss_active)) {
/* An indirect jump so that we still trigger the debug exception. */
gen_update_pc(s, diff);
@@ -2653,9 +2657,9 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t
dest, int tbno)
}
}
-static inline void gen_jmp(DisasContext *s, uint32_t dest)
+static inline void gen_jmp(DisasContext *s, target_long diff)
{
- gen_jmp_tb(s, dest, 0);
+ gen_jmp_tb(s, diff, 0);
}
static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
@@ -8322,7 +8326,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
static bool trans_B(DisasContext *s, arg_i *a)
{
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
@@ -8337,14 +8341,14 @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci
*a)
return true;
}
arm_skip_unless(s, a->cond);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
static bool trans_BL(DisasContext *s, arg_i *a)
{
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
@@ -8364,7 +8368,8 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
}
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
store_cpu_field_constant(!s->thumb, thumb);
- gen_jmp(s, (read_pc(s) & ~3) + a->imm);
+ /* This jump is computed from an aligned PC: subtract off the low bits. */
+ gen_jmp(s, jmp_diff(s, a->imm - (s->pc_curr & 3)));
return true;
}
@@ -8525,10 +8530,10 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
* when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
*/
}
- gen_jmp_tb(s, s->base.pc_next, 1);
+ gen_jmp_tb(s, curr_insn_len(s), 1);
gen_set_label(nextlabel);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
@@ -8608,7 +8613,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
if (a->f) {
/* Loop-forever: just jump back to the loop start */
- gen_jmp(s, read_pc(s) - a->imm);
+ gen_jmp(s, jmp_diff(s, -a->imm));
return true;
}
@@ -8639,7 +8644,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
tcg_temp_free_i32(decr);
}
/* Jump back to the loop start */
- gen_jmp(s, read_pc(s) - a->imm);
+ gen_jmp(s, jmp_diff(s, -a->imm));
gen_set_label(loopend);
if (a->tp) {
@@ -8647,7 +8652,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
}
/* End TB, continuing to following insn */
- gen_jmp_tb(s, s->base.pc_next, 1);
+ gen_jmp_tb(s, curr_insn_len(s), 1);
return true;
}
@@ -8746,7 +8751,7 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE,
tmp, 0, s->condlabel);
tcg_temp_free_i32(tmp);
- gen_jmp(s, read_pc(s) + a->imm);
+ gen_jmp(s, jmp_diff(s, a->imm));
return true;
}
--
2.25.1
- [PULL 02/24] target/arm: update the cortex-a15 MIDR to latest rev, (continued)
- [PULL 02/24] target/arm: update the cortex-a15 MIDR to latest rev, Peter Maydell, 2022/10/20
- [PULL 23/24] target/arm: Enable TARGET_TB_PCREL, Peter Maydell, 2022/10/20
- [PULL 07/24] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx, Peter Maydell, 2022/10/20
- [PULL 11/24] target/arm: Move be test for regime into S1TranslateResult, Peter Maydell, 2022/10/20
- [PULL 06/24] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Peter Maydell, 2022/10/20
- [PULL 10/24] target/arm: Plumb debug into S1Translate, Peter Maydell, 2022/10/20
- [PULL 15/24] target/arm: Introduce curr_insn_len, Peter Maydell, 2022/10/20
- [PULL 17/24] target/arm: Change gen_*set_pc_im to gen_*update_pc, Peter Maydell, 2022/10/20
- [PULL 04/24] target/arm: Use probe_access_full for MTE, Peter Maydell, 2022/10/20
- [PULL 19/24] target/arm: Remove gen_exception_internal_insn pc argument, Peter Maydell, 2022/10/20
- [PULL 20/24] target/arm: Change gen_jmp* to work on displacements,
Peter Maydell <=
- [PULL 22/24] target/arm: Introduce gen_pc_plus_diff for aarch32, Peter Maydell, 2022/10/20
- [PULL 16/24] target/arm: Change gen_goto_tb to work on displacements, Peter Maydell, 2022/10/20
- [PULL 18/24] target/arm: Change gen_exception_insn* to work on displacements, Peter Maydell, 2022/10/20
- [PULL 24/24] hw/ide/microdrive: Use device_cold_reset() for self-resets, Peter Maydell, 2022/10/20
- [PULL 08/24] target/arm: Restrict tlb flush from vttbr_write to vmid change, Peter Maydell, 2022/10/20
- [PULL 12/24] target/arm: Use softmmu tlbs for page table walking, Peter Maydell, 2022/10/20
- [PULL 13/24] target/arm: Split out get_phys_addr_twostage, Peter Maydell, 2022/10/20
- [PULL 14/24] target/arm: Use bool consistently for get_phys_addr subroutines, Peter Maydell, 2022/10/20
- [PULL 21/24] target/arm: Introduce gen_pc_plus_diff for aarch64, Peter Maydell, 2022/10/20