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[PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters
From: |
Richard Henderson |
Subject: |
[PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters |
Date: |
Sat, 1 Oct 2022 09:23:08 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 2 ++
target/arm/helper.c | 8 +++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a50189e2e4..e95b6b1b8f 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1014,6 +1014,8 @@ typedef struct ARMVAParameters {
bool using64k : 1;
bool tsz_oob : 1; /* tsz has been clamped to legal range */
bool ds : 1;
+ bool ha : 1;
+ bool hd : 1;
} ARMVAParameters;
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 19a03eb200..70ae3816b9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10280,7 +10280,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
ARMMMUIdx mmu_idx, bool data)
{
uint64_t tcr = regime_tcr(env, mmu_idx);
- bool epd, hpd, using16k, using64k, tsz_oob, ds;
+ bool epd, hpd, using16k, using64k, tsz_oob, ds, ha, hd;
int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
ARMCPU *cpu = env_archcpu(env);
@@ -10298,6 +10298,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
epd = false;
sh = extract32(tcr, 12, 2);
ps = extract32(tcr, 16, 3);
+ ha = extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu);
+ hd = extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu);
ds = extract64(tcr, 32, 1);
} else {
/*
@@ -10322,6 +10324,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
hpd = extract64(tcr, 42, 1);
}
ps = extract64(tcr, 32, 3);
+ ha = extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu);
+ hd = extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu);
ds = extract64(tcr, 59, 1);
}
@@ -10393,6 +10397,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
.using64k = using64k,
.tsz_oob = tsz_oob,
.ds = ds,
+ .ha = ha,
+ .hd = ha & hd,
};
}
--
2.34.1
- Re: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking, (continued)
- [PATCH v3 28/42] target/arm: Split out get_phys_addr_twostage, Richard Henderson, 2022/10/01
- [PATCH v3 29/42] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/10/01
- [PATCH v3 30/42] target/arm: Add ptw_idx argument to S1_ptw_translate, Richard Henderson, 2022/10/01
- [PATCH v3 31/42] target/arm: Add isar predicates for FEAT_HAFDBS, Richard Henderson, 2022/10/01
- [PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters,
Richard Henderson <=
- [PATCH v3 33/42] target/arm: Split out S1TranslateResult type, Richard Henderson, 2022/10/01
- [PATCH v3 34/42] target/arm: Move be test for regime into S1TranslateResult, Richard Henderson, 2022/10/01
- [PATCH v3 35/42] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Richard Henderson, 2022/10/01