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[PATCH v2 1/2] hw/intc: sifive_plic: fix hard-coded max priority level
From: |
Jim Shu |
Subject: |
[PATCH v2 1/2] hw/intc: sifive_plic: fix hard-coded max priority level |
Date: |
Fri, 30 Sep 2022 12:32:38 +0000 |
The maximum priority level is hard-coded when writing to interrupt
priority register. However, when writing to priority threshold register,
the maximum priority level is from num_priorities Property which is
configured by platform.
Also change interrupt priority register to use num_priorities Property
in maximum priority level.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/intc/sifive_plic.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index af4ae3630e..f864efa761 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -180,8 +180,10 @@ static void sifive_plic_write(void *opaque, hwaddr addr,
uint64_t value,
if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
- plic->source_priority[irq] = value & 7;
- sifive_plic_update(plic);
+ if (value <= plic->num_priorities) {
+ plic->source_priority[irq] = value;
+ sifive_plic_update(plic);
+ }
} else if (addr_between(addr, plic->pending_base,
plic->num_sources >> 3)) {
qemu_log_mask(LOG_GUEST_ERROR,
--
2.17.1