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[PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build t
From: |
Alistair Francis |
Subject: |
[PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content |
Date: |
Tue, 27 Sep 2022 16:30:56 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Introduce build_tdata1() to build tdata1 register content, which can be
shared among all types of triggers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
[bmeng: moved RV{32,64}_DATA_MASK definition to this patch]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220909134215.1843865-3-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.h | 2 ++
target/riscv/debug.c | 15 ++++++++++-----
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index 72e4edcd8c..c422553c27 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -56,9 +56,11 @@ typedef struct {
#define RV32_TYPE(t) ((uint32_t)(t) << 28)
#define RV32_TYPE_MASK (0xf << 28)
#define RV32_DMODE BIT(27)
+#define RV32_DATA_MASK 0x7ffffff
#define RV64_TYPE(t) ((uint64_t)(t) << 60)
#define RV64_TYPE_MASK (0xfULL << 60)
#define RV64_DMODE BIT_ULL(59)
+#define RV64_DATA_MASK 0x7ffffffffffffff
/* mcontrol field masks */
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 9dd468753a..45aae87ec3 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -95,18 +95,23 @@ static inline target_ulong get_trigger_type(CPURISCVState
*env,
return extract_trigger_type(env, tdata1);
}
-static inline target_ulong trigger_type(CPURISCVState *env,
- trigger_type_t type)
+static inline target_ulong build_tdata1(CPURISCVState *env,
+ trigger_type_t type,
+ bool dmode, target_ulong data)
{
target_ulong tdata1;
switch (riscv_cpu_mxl(env)) {
case MXL_RV32:
- tdata1 = RV32_TYPE(type);
+ tdata1 = RV32_TYPE(type) |
+ (dmode ? RV32_DMODE : 0) |
+ (data & RV32_DATA_MASK);
break;
case MXL_RV64:
case MXL_RV128:
- tdata1 = RV64_TYPE(type);
+ tdata1 = RV64_TYPE(type) |
+ (dmode ? RV64_DMODE : 0) |
+ (data & RV64_DATA_MASK);
break;
default:
g_assert_not_reached();
@@ -495,7 +500,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
void riscv_trigger_init(CPURISCVState *env)
{
- target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
+ target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
int i;
/* init to type 2 triggers */
--
2.37.3
- [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub, (continued)
- [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/27
- [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Alistair Francis, 2022/09/27
- [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type, Alistair Francis, 2022/09/27
- [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, Alistair Francis, 2022/09/27
- [PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger, Alistair Francis, 2022/09/27
- [PULL v2 18/22] target/riscv: debug: Create common trigger actions function, Alistair Francis, 2022/09/27
- [PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written, Alistair Francis, 2022/09/27
- [PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code, Alistair Francis, 2022/09/27
- [PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR, Alistair Francis, 2022/09/27
- [PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered, Alistair Francis, 2022/09/27
- [PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content,
Alistair Francis <=
- [PULL v2 20/22] target/riscv: debug: Add initial support of type 6 trigger, Alistair Francis, 2022/09/27
- Re: [PULL v2 00/22] riscv-to-apply queue, Stefan Hajnoczi, 2022/09/27