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[PATCH v5 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks(
From: |
BALATON Zoltan |
Subject: |
[PATCH v5 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks() |
Date: |
Sun, 18 Sep 2022 22:24:42 +0200 (CEST) |
Do not exit from ppc4xx_sdram_banks() but report error via an errp
parameter instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc4xx_sdram.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 2ef363d5e6..543d47aec3 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -53,10 +53,12 @@
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC.
*/
-static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
+static bool ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
- const ram_addr_t sdram_bank_sizes[])
+ const ram_addr_t sdram_bank_sizes[],
+ Error **errp)
{
+ ERRP_GUARD();
ram_addr_t size_left = memory_region_size(ram);
ram_addr_t base = 0;
ram_addr_t bank_size;
@@ -94,14 +96,16 @@ static void ppc4xx_sdram_banks(MemoryRegion *ram, int
nr_banks,
sdram_bank_sizes[i] / MiB,
sdram_bank_sizes[i + 1] ? ", " : "");
}
- error_report("at most %d bank%s of %s MiB each supported",
- nr_banks, nr_banks == 1 ? "" : "s", s->str);
- error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
- used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
+ error_setg(errp, "Invalid SDRAM banks");
+ error_append_hint(errp, "at most %d bank%s of %s MiB each supported\n",
+ nr_banks, nr_banks == 1 ? "" : "s", s->str);
+ error_append_hint(errp, "Possible valid RAM size: %" PRIi64 " MiB\n",
+ used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
g_string_free(s, true);
- exit(EXIT_FAILURE);
+ return false;
}
+ return true;
}
static void sdram_bank_map(Ppc4xxSdramBank *bank)
@@ -400,7 +404,10 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev,
Error **errp)
error_setg(errp, "Missing dram memory region");
return;
}
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
+ valid_bank_sizes, errp)) {
+ return;
+ }
for (i = 0; i < s->nbanks; i++) {
if (s->bank[i].size) {
s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);
@@ -663,7 +670,10 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev,
Error **errp)
error_setg(errp, "Missing dram memory region");
return;
}
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
+ valid_bank_sizes, errp)) {
+ return;
+ }
for (i = 0; i < s->nbanks; i++) {
if (s->bank[i].size) {
s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);
--
2.30.4
- [PATCH v5 07/21] ppc4xx_sdram: QOM'ify, (continued)
- [PATCH v5 07/21] ppc4xx_sdram: QOM'ify, BALATON Zoltan, 2022/09/18
- [PATCH v5 08/21] ppc4xx_sdram: Drop extra zeros for readability, BALATON Zoltan, 2022/09/18
- [PATCH v5 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse, BALATON Zoltan, 2022/09/18
- [PATCH v5 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM, BALATON Zoltan, 2022/09/18
- [PATCH v5 11/21] ppc440_sdram: Get rid of the init RAM hack, BALATON Zoltan, 2022/09/18
- [PATCH v5 12/21] ppc440_sdram: Rename local variable for readability, BALATON Zoltan, 2022/09/18
- [PATCH v5 13/21] ppc4xx_sdram: Rename functions to prevent name clashes, BALATON Zoltan, 2022/09/18
- [PATCH v5 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init, BALATON Zoltan, 2022/09/18
- [PATCH v5 15/21] ppc440_sdram: QOM'ify, BALATON Zoltan, 2022/09/18
- [PATCH v5 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks(),
BALATON Zoltan <=
- [PATCH v5 17/21] ppc4xx_sdram: Use hwaddr for memory bank size, BALATON Zoltan, 2022/09/18
- [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together, BALATON Zoltan, 2022/09/18
- [PATCH v5 18/21] ppc4xx_sdram: Rename local state variable for brevity, BALATON Zoltan, 2022/09/18
- [PATCH v5 19/21] ppc4xx_sdram: Generalise bank setup, BALATON Zoltan, 2022/09/18
- [PATCH v5 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling, BALATON Zoltan, 2022/09/18
- Re: [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups, Philippe Mathieu-Daudé, 2022/09/18