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[PATCH] hw/pci-bridge: Fix brace Werror with clang 6.0.0
From: |
Chenyi Qiang |
Subject: |
[PATCH] hw/pci-bridge: Fix brace Werror with clang 6.0.0 |
Date: |
Thu, 1 Sep 2022 18:08:10 +0800 |
Two warnings are:
/hw/pci-bridge/cxl_downstream.c:101:51: error: suggest braces
around initialization of subobject [-Werror,-Wmissing-braces]
dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
^
{}
/hw/pci-bridge/cxl_root_port.c:62:51: error: suggest braces
around initialization of subobject [-Werror,-Wmissing-braces]
dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
^
{}
The original code is correct, just to work around clang's bogus warning.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
hw/pci-bridge/cxl_downstream.c | 2 +-
hw/pci-bridge/cxl_root_port.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
index a361e519d0..8e536f193b 100644
--- a/hw/pci-bridge/cxl_downstream.c
+++ b/hw/pci-bridge/cxl_downstream.c
@@ -98,7 +98,7 @@ static void build_dvsecs(CXLComponentState *cxl)
{
uint8_t *dvsec;
- dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
+ dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ };
cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT,
EXTENSIONS_PORT_DVSEC_LENGTH,
EXTENSIONS_PORT_DVSEC,
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index fb213fa06e..e959f82086 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -59,7 +59,7 @@ static void build_dvsecs(CXLComponentState *cxl)
{
uint8_t *dvsec;
- dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
+ dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ };
cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
EXTENSIONS_PORT_DVSEC_LENGTH,
EXTENSIONS_PORT_DVSEC,
--
2.17.1
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