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[PULL 036/117] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz
From: |
Peter Maydell |
Subject: |
[PULL 036/117] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz |
Date: |
Mon, 30 May 2022 17:05:47 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Convert SVE translation functions directly using
gen_gvec_fn_arg_zzz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-34-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 66 +++++++-------------------------------
1 file changed, 11 insertions(+), 55 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 2dbf2961283..ddb34cad8e9 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -376,25 +376,10 @@ const uint64_t pred_esz_masks[4] = {
*** SVE Logical - Unpredicated Group
*/
-static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
-}
-
-static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
-}
-
-static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
-}
-
-static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
-}
+TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a)
+TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a)
+TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a)
+TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a)
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
{
@@ -706,35 +691,12 @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
*** SVE Integer Arithmetic - Unpredicated Group
*/
-static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
-}
-
-static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
-}
-
-static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
-}
-
-static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
-}
-
-static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
-}
-
-static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
-}
+TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a)
+TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a)
+TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a)
+TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a)
+TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a)
+TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a)
/*
*** SVE Integer Arithmetic - Binary Predicated Group
@@ -6420,13 +6382,7 @@ static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz
*a)
* SVE2 Integer Multiply - Unpredicated
*/
-static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
-{
- if (!dc_isar_feature(aa64_sve2, s)) {
- return false;
- }
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_mul, a);
-}
+TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a)
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
--
2.25.1
- [PULL 030/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz, (continued)
- [PULL 030/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz, Peter Maydell, 2022/05/30
- [PULL 029/117] target/arm: Introduce gen_gvec_ool_arg_zpzz, Peter Maydell, 2022/05/30
- [PULL 024/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz, Peter Maydell, 2022/05/30
- [PULL 034/117] target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz, Peter Maydell, 2022/05/30
- [PULL 039/117] target/arm: Introduce gen_gvec_fn_arg_zzzz, Peter Maydell, 2022/05/30
- [PULL 026/117] target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi, Peter Maydell, 2022/05/30
- [PULL 031/117] target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool, Peter Maydell, 2022/05/30
- [PULL 033/117] target/arm: Move null function and sve check into gen_gvec_fn_zzz, Peter Maydell, 2022/05/30
- [PULL 032/117] target/arm: Merge gen_gvec_fn_zz into do_mov_z, Peter Maydell, 2022/05/30
- [PULL 035/117] target/arm: More use of gen_gvec_fn_arg_zzz, Peter Maydell, 2022/05/30
- [PULL 036/117] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz,
Peter Maydell <=
- [PULL 040/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn, Peter Maydell, 2022/05/30
- [PULL 028/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzp, Peter Maydell, 2022/05/30
- [PULL 041/117] target/arm: Introduce gen_gvec_fn_zzi, Peter Maydell, 2022/05/30
- [PULL 037/117] target/arm: Use TRANS_FEAT for do_sve2_fn_zzz, Peter Maydell, 2022/05/30
- [PULL 047/117] target/arm: Use TRANS_FEAT for do_shift_imm, Peter Maydell, 2022/05/30
- [PULL 053/117] target/arm: Use TRANS_FEAT for do_adr, Peter Maydell, 2022/05/30
- [PULL 055/117] target/arm: Use TRANS_FEAT for RDFFR, WRFFR, Peter Maydell, 2022/05/30
- [PULL 057/117] target/arm: Use TRANS_FEAT for do_EXT, Peter Maydell, 2022/05/30
- [PULL 038/117] target/arm: Use TRANS_FEAT for RAX1, Peter Maydell, 2022/05/30
- [PULL 044/117] target/arm: Introduce gen_gvec_fn_arg_zzi, Peter Maydell, 2022/05/30