[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH RESEND 08/10] target/ppc: implement addg6s
From: |
Víctor Colombo |
Subject: |
[PATCH RESEND 08/10] target/ppc: implement addg6s |
Date: |
Tue, 17 May 2022 13:47:42 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following Power ISA v2.06 instruction:
addg6s: Add and Generate Sixes
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/fixedpoint-impl.c.inc | 35 ++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a3e87a0867..9d87dd35c0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -296,6 +296,10 @@ CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
PDEPD 011111 ..... ..... ..... 0010011100 - @X
PEXTD 011111 ..... ..... ..... 0010111100 - @X
+## BCD Assist
+
+ADDG6S 011111 ..... ..... ..... - 001001010 - @X
+
### Float-Point Load Instructions
LFS 110000 ..... ..... ................ @D
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..62f5027b5b 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -492,3 +492,38 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
+{
+ const uint64_t nibbles = 0x0f0f0f0f0f0f0f0fULL,
+ carry_bits = 0x1010101010101010ULL;
+ TCGv t0, t1, t2;
+
+ REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[a->ra], nibbles);
+ tcg_gen_andi_tl(t1, cpu_gpr[a->rb], nibbles);
+ tcg_gen_add_tl(t0, t0, t1);
+ tcg_gen_andi_tl(t0, t0, carry_bits);
+ tcg_gen_shri_tl(t0, t0, 4);
+
+ tcg_gen_shri_tl(t1, cpu_gpr[a->ra], 4);
+ tcg_gen_shri_tl(t2, cpu_gpr[a->rb], 4);
+ tcg_gen_andi_tl(t1, t1, nibbles);
+ tcg_gen_andi_tl(t2, t2, nibbles);
+ tcg_gen_add_tl(t1, t1, t2);
+ tcg_gen_andi_tl(t1, t1, carry_bits);
+
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_muli_tl(cpu_gpr[a->rt], t0, 6);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+
+ return true;
+}
--
2.25.1
- [PATCH RESEND 03/10] target/ppc: Move mffsl to decodetree, (continued)
- [PATCH RESEND 03/10] target/ppc: Move mffsl to decodetree, Víctor Colombo, 2022/05/17
- [PATCH RESEND 04/10] target/ppc: Move mffsce to decodetree, Víctor Colombo, 2022/05/17
- [PATCH RESEND 06/10] target/ppc: Implement mffscdrn[i] instructions, Víctor Colombo, 2022/05/17
- [PATCH RESEND 05/10] target/ppc: Move mffscrn[i] to decodetree, Víctor Colombo, 2022/05/17
- [PATCH RESEND 07/10] target/ppc: Add flag for ISA v2.06 BCDA instructions, Víctor Colombo, 2022/05/17
- [PATCH RESEND 08/10] target/ppc: implement addg6s,
Víctor Colombo <=
- [PATCH RESEND 09/10] target/ppc: implement cbcdtd, Víctor Colombo, 2022/05/17
- [PATCH RESEND 10/10] target/ppc: implement cdtbcd, Víctor Colombo, 2022/05/17