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[PULL 32/91] pci/pcie_port: Add pci_find_port_by_pn()
From: |
Michael S. Tsirkin |
Subject: |
[PULL 32/91] pci/pcie_port: Add pci_find_port_by_pn() |
Date: |
Mon, 16 May 2022 06:37:29 -0400 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-31-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/pci/pcie_port.h | 2 ++
hw/pci/pcie_port.c | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h
index e25b289ce8..7b8193061a 100644
--- a/include/hw/pci/pcie_port.h
+++ b/include/hw/pci/pcie_port.h
@@ -39,6 +39,8 @@ struct PCIEPort {
void pcie_port_init_reg(PCIDevice *d);
+PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn);
+
#define TYPE_PCIE_SLOT "pcie-slot"
OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT)
diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
index e95c1e5519..687e4e763a 100644
--- a/hw/pci/pcie_port.c
+++ b/hw/pci/pcie_port.c
@@ -136,6 +136,31 @@ static void pcie_port_class_init(ObjectClass *oc, void
*data)
device_class_set_props(dc, pcie_port_props);
}
+PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn)
+{
+ int devfn;
+
+ for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
+ PCIDevice *d = bus->devices[devfn];
+ PCIEPort *port;
+
+ if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
+ continue;
+ }
+
+ if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
+ continue;
+ }
+
+ port = PCIE_PORT(d);
+ if (port->port == pn) {
+ return d;
+ }
+ }
+
+ return NULL;
+}
+
static const TypeInfo pcie_port_type_info = {
.name = TYPE_PCIE_PORT,
.parent = TYPE_PCI_BRIDGE,
--
MST
- [PULL 22/91] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, (continued)
- [PULL 22/91] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Michael S. Tsirkin, 2022/05/16
- [PULL 23/91] hw/cxl/device: Implement get/set Label Storage Area (LSA), Michael S. Tsirkin, 2022/05/16
- [PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests, Michael S. Tsirkin, 2022/05/16
- [PULL 25/91] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Michael S. Tsirkin, 2022/05/16
- [PULL 26/91] acpi/cxl: Add _OSC implementation (9.14.2), Michael S. Tsirkin, 2022/05/16
- [PULL 27/91] acpi/cxl: Create the CEDT (9.14.1), Michael S. Tsirkin, 2022/05/16
- [PULL 28/91] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Michael S. Tsirkin, 2022/05/16
- [PULL 29/91] hw/cxl/host: Add support for CXL Fixed Memory Windows., Michael S. Tsirkin, 2022/05/16
- [PULL 30/91] acpi/cxl: Introduce CFMWS structures in CEDT, Michael S. Tsirkin, 2022/05/16
- [PULL 31/91] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Michael S. Tsirkin, 2022/05/16
- [PULL 32/91] pci/pcie_port: Add pci_find_port_by_pn(),
Michael S. Tsirkin <=
- [PULL 33/91] CXL/cxl_component: Add cxl_get_hb_cstate(), Michael S. Tsirkin, 2022/05/16
- [PULL 35/91] cxl/cxl-host: Add memops for CFMWS region., Michael S. Tsirkin, 2022/05/16
- [PULL 34/91] mem/cxl_type3: Add read and write functions for associated hostmem., Michael S. Tsirkin, 2022/05/16
- [PULL 36/91] hw/cxl/component Add a dumb HDM decoder handler, Michael S. Tsirkin, 2022/05/16
- [PULL 37/91] i386/pc: Enable CXL fixed memory windows, Michael S. Tsirkin, 2022/05/16
- [PULL 39/91] qtests/bios-tables-test: Add a test for CXL emulation., Michael S. Tsirkin, 2022/05/16
- [PULL 38/91] tests/acpi: q35: Allow addition of a CXL test., Michael S. Tsirkin, 2022/05/16
- [PULL 40/91] tests/acpi: Add tables for CXL emulation., Michael S. Tsirkin, 2022/05/16
- [PULL 41/91] qtest/cxl: Add more complex test cases with CFMWs, Michael S. Tsirkin, 2022/05/16
- [PULL 42/91] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Michael S. Tsirkin, 2022/05/16