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[PULL 14/91] hw/pci/cxl: Create a CXL bus type
From: |
Michael S. Tsirkin |
Subject: |
[PULL 14/91] hw/pci/cxl: Create a CXL bus type |
Date: |
Mon, 16 May 2022 06:36:22 -0400 |
From: Ben Widawsky <ben.widawsky@intel.com>
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the bus to the
correct type. This is less code and useful for debugging via simply
looking at the flags.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-13-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/pci/pci_bus.h | 7 +++++++
hw/pci-bridge/pci_expander_bridge.c | 9 ++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 347440d42c..eb94e7e85c 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -24,6 +24,8 @@ enum PCIBusFlags {
PCI_BUS_IS_ROOT = 0x0001,
/* PCIe extended configuration space is accessible on this bus */
PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002,
+ /* This is a CXL Type BUS */
+ PCI_BUS_CXL = 0x0004,
};
struct PCIBus {
@@ -53,6 +55,11 @@ struct PCIBus {
Notifier machine_done;
};
+static inline bool pci_bus_is_cxl(PCIBus *bus)
+{
+ return !!(bus->flags & PCI_BUS_CXL);
+}
+
static inline bool pci_bus_is_root(PCIBus *bus)
{
return !!(bus->flags & PCI_BUS_IS_ROOT);
diff --git a/hw/pci-bridge/pci_expander_bridge.c
b/hw/pci-bridge/pci_expander_bridge.c
index d4514227a8..a6caa1e7b5 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -24,7 +24,7 @@
#include "hw/boards.h"
#include "qom/object.h"
-enum BusType { PCI, PCIE };
+enum BusType { PCI, PCIE, CXL };
#define TYPE_PXB_BUS "pxb-bus"
typedef struct PXBBus PXBBus;
@@ -35,6 +35,10 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS,
DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS,
TYPE_PXB_PCIE_BUS)
+#define TYPE_PXB_CXL_BUS "pxb-cxl-bus"
+DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS,
+ TYPE_PXB_CXL_BUS)
+
struct PXBBus {
/*< private >*/
PCIBus parent_obj;
@@ -251,6 +255,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum
BusType type,
ds = qdev_new(TYPE_PXB_HOST);
if (type == PCIE) {
bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
+ } else if (type == CXL) {
+ bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS);
+ bus->flags |= PCI_BUS_CXL;
} else {
bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0,
TYPE_PXB_BUS);
bds = qdev_new("pci-bridge");
--
MST
- [PULL 05/91] MAINTAINERS: Add entry for Compute Express Link Emulation, (continued)
- [PULL 05/91] MAINTAINERS: Add entry for Compute Express Link Emulation, Michael S. Tsirkin, 2022/05/16
- [PULL 04/91] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5), Michael S. Tsirkin, 2022/05/16
- [PULL 07/91] hw/cxl/device: Implement the CAP array (8.2.8.1-2), Michael S. Tsirkin, 2022/05/16
- [PULL 08/91] hw/cxl/device: Implement basic mailbox (8.2.8.4), Michael S. Tsirkin, 2022/05/16
- [PULL 06/91] hw/cxl/device: Introduce a CXL device (8.2.8), Michael S. Tsirkin, 2022/05/16
- [PULL 09/91] hw/cxl/device: Add memory device utilities, Michael S. Tsirkin, 2022/05/16
- [PULL 11/91] hw/cxl/device: Timestamp implementation (8.2.9.3), Michael S. Tsirkin, 2022/05/16
- [PULL 10/91] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1), Michael S. Tsirkin, 2022/05/16
- [PULL 12/91] hw/cxl/device: Add log commands (8.2.9.4) + CEL, Michael S. Tsirkin, 2022/05/16
- [PULL 13/91] hw/pxb: Use a type for realizing expanders, Michael S. Tsirkin, 2022/05/16
- [PULL 14/91] hw/pci/cxl: Create a CXL bus type,
Michael S. Tsirkin <=
- [PULL 15/91] cxl: Machine level control on whether CXL support is enabled, Michael S. Tsirkin, 2022/05/16
- [PULL 17/91] qtest/cxl: Introduce initial test for pxb-cxl only., Michael S. Tsirkin, 2022/05/16
- [PULL 16/91] hw/pxb: Allow creation of a CXL PXB (host bridge), Michael S. Tsirkin, 2022/05/16
- [PULL 18/91] hw/cxl/rp: Add a root port, Michael S. Tsirkin, 2022/05/16
- [PULL 19/91] hw/cxl/device: Add a memory device (8.2.8.5), Michael S. Tsirkin, 2022/05/16
- [PULL 20/91] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Michael S. Tsirkin, 2022/05/16
- [PULL 21/91] hw/cxl/device: Add some trivial commands, Michael S. Tsirkin, 2022/05/16
- [PULL 22/91] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Michael S. Tsirkin, 2022/05/16
- [PULL 23/91] hw/cxl/device: Implement get/set Label Storage Area (LSA), Michael S. Tsirkin, 2022/05/16
- [PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests, Michael S. Tsirkin, 2022/05/16