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[PATCH 3/5] target/riscv: Change "G" expansion
From: |
Tsukasa OI |
Subject: |
[PATCH 3/5] target/riscv: Change "G" expansion |
Date: |
Fri, 13 May 2022 18:45:48 +0900 |
On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
be (virtually) enabled as well, it should be safe to change its expansion.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3ea68d5cd7..0854ca9103 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -598,13 +598,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
cpu->cfg.ext_a && cpu->cfg.ext_f &&
- cpu->cfg.ext_d)) {
- warn_report("Setting G will also set IMAFD");
+ cpu->cfg.ext_d &&
+ cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+ warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_a = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.ext_ifencei = true;
}
if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
--
2.34.1
- [PATCH 0/5] target/riscv: Enhanced ISA extension checks, Tsukasa OI, 2022/05/13
- [PATCH 1/5] target/riscv: Fix "G" extension expansion typing, Tsukasa OI, 2022/05/13
- [PATCH 2/5] target/riscv: Disable "G" by default, Tsukasa OI, 2022/05/13
- [PATCH 3/5] target/riscv: Change "G" expansion,
Tsukasa OI <=
- [PATCH 4/5] target/riscv: FP extension requirements, Tsukasa OI, 2022/05/13
- [PATCH 5/5] target/riscv: Move/refactor ISA extension checks, Tsukasa OI, 2022/05/13
- [PATCH v2 0/5] target/riscv: Enhanced ISA extension checks, Tsukasa OI, 2022/05/14