[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 4/5] hw/intc/arm_gicv3: Use correct number of priority bits f
From: |
Peter Maydell |
Subject: |
Re: [PATCH 4/5] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU |
Date: |
Tue, 10 May 2022 10:09:24 +0100 |
On Mon, 9 May 2022 at 23:55, ishii.shuuichir@fujitsu.com
<ishii.shuuichir@fujitsu.com> wrote:
>
> Hi, Peter.
>
> > Shuuichirou, Itaru: do either of you know the right setting for the A64FX
> > for this? If
> > you can find what the hardware value of the ICC_CTLR_EL3 or ICC_CTLR_EL1
> > register is (more specifically, the PRIBits subfield) that should be enough
> > to tell
> > us.
>
> The value of the PRIbits field in the A64FX is 0x4.
> Therefore, the following values is fine.
>
> > > + cpu->gic_pribits = 5;
Great, thanks very much for confirming this.
-- PMM
- [PATCH 0/5] gicv3: Use right number of prio bits for the CPU, Peter Maydell, 2022/05/06
- [PATCH 1/5] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1, Peter Maydell, 2022/05/06
- [PATCH 2/5] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant, Peter Maydell, 2022/05/06
- [PATCH 3/5] hw/intc/arm_gicv3: Support configurable number of physical priority bits, Peter Maydell, 2022/05/06
- [PATCH 5/5] hw/intc/arm_gicv3: Provide ich_num_aprs(), Peter Maydell, 2022/05/06
- [PATCH 4/5] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU, Peter Maydell, 2022/05/06
- Re: [PATCH 0/5] gicv3: Use right number of prio bits for the CPU, Richard Henderson, 2022/05/07