[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 2/2] hw/nvme: support smart AEN
From: |
zhenwei pi |
Subject: |
[PATCH 2/2] hw/nvme: support smart AEN |
Date: |
Sat, 7 May 2022 15:26:44 +0800 |
Support smart AEN on controller side, if the guest side enables this
feature, after injecting smart critical warning, also raise AER.
This can be tested by:
virsh qemu-monitor-command vm '{ "execute": "qom-set", "arguments":
{ "path": "/machine/peripheral/nvme0",
"property": "smart_critical_warning", "value":1 } }'
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
---
hw/nvme/ctrl.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 03760ddeae..8236a746c8 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -6707,6 +6707,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice
*pci_dev)
NvmeIdCtrl *id = &n->id_ctrl;
uint8_t *pci_conf = pci_dev->config;
uint64_t cap = ldq_le_p(&n->bar.cap);
+ uint32_t supported_oaes;
id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
@@ -6716,7 +6717,13 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice
*pci_dev)
id->cntlid = cpu_to_le16(n->cntlid);
- id->oaes = cpu_to_le32(NVME_OAES_NS_ATTR);
+ supported_oaes = NVME_OAES_SMART_SPARE | NVME_OAES_SMART_TEMPERATURE |
+ NVME_OAES_SMART_RELIABILITY |
+ NVME_OAES_SMART_MEDIA_READ_ONLY |
+ NVME_OAES_SMART_FAILED_VOLATILE_MEDIA |
+ NVME_OAES_SMART_PMR_UNRELIABLE |
+ NVME_OAES_NS_ATTR;
+ id->oaes = cpu_to_le32(supported_oaes);
id->ctratt |= cpu_to_le32(NVME_CTRATT_ELBAS);
id->rab = 6;
--
2.20.1