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[PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashta
From: |
Peter Maydell |
Subject: |
[PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable |
Date: |
Thu, 5 May 2022 10:11:38 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Move the computation of key to the top of the function.
Hoist the resolution of cp as well, as an input to the
computation of key.
This will be required by a subsequent patch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d92fd23445b..cbc873e3e60 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8509,8 +8509,34 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
ARMCPRegInfo *r2;
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+ int cp = r->cp;
size_t name_len;
+ switch (state) {
+ case ARM_CP_STATE_AA32:
+ /* We assume it is a cp15 register if the .cp field is left unset. */
+ if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
+ cp = 15;
+ }
+ key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
+ break;
+ case ARM_CP_STATE_AA64:
+ /*
+ * To allow abbreviation of ARMCPRegInfo definitions, we treat
+ * cp == 0 as equivalent to the value for "standard guest-visible
+ * sysreg". STATE_BOTH definitions are also always "standard sysreg"
+ * in their AArch64 view (the .cp value may be non-zero for the
+ * benefit of the AArch32 view).
+ */
+ if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+ cp = CP_REG_ARM64_SYSREG_CP;
+ }
+ key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
/* Combine cpreg and name into one allocation. */
name_len = strlen(name) + 1;
r2 = g_malloc(sizeof(*r2) + name_len);
@@ -8554,12 +8580,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
}
if (r->state == ARM_CP_STATE_BOTH) {
- /* We assume it is a cp15 register if the .cp field is left unset.
- */
- if (r2->cp == 0) {
- r2->cp = 15;
- }
-
#if HOST_BIG_ENDIAN
if (r2->fieldoffset) {
r2->fieldoffset += sizeof(uint32_t);
@@ -8567,22 +8587,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
#endif
}
}
- if (state == ARM_CP_STATE_AA64) {
- /* To allow abbreviation of ARMCPRegInfo
- * definitions, we treat cp == 0 as equivalent to
- * the value for "standard guest-visible sysreg".
- * STATE_BOTH definitions are also always "standard
- * sysreg" in their AArch64 view (the .cp value may
- * be non-zero for the benefit of the AArch32 view).
- */
- if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
- r2->cp = CP_REG_ARM64_SYSREG_CP;
- }
- key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
- r2->opc0, opc1, opc2);
- } else {
- key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
- }
if (opaque) {
r2->opaque = opaque;
}
@@ -8593,6 +8597,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
/* Make sure reginfo passed to helpers for wildcarded regs
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
*/
+ r2->cp = cp;
r2->crm = crm;
r2->opc1 = opc1;
r2->opc2 = opc2;
--
2.25.1
- [PULL 10/23] target/arm: Name CPSecureState type, (continued)
- [PULL 10/23] target/arm: Name CPSecureState type, Peter Maydell, 2022/05/05
- [PULL 09/23] target/arm: Name CPState type, Peter Maydell, 2022/05/05
- [PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h, Peter Maydell, 2022/05/05
- [PULL 13/23] target/arm: Merge allocation of the cpreg and its name, Peter Maydell, 2022/05/05
- [PULL 15/23] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases, Peter Maydell, 2022/05/05
- [PULL 17/23] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 18/23] target/arm: Perform override check early in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 12/23] target/arm: Store cpregs key in the hash table directly, Peter Maydell, 2022/05/05
- [PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable,
Peter Maydell <=
- [PULL 16/23] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 20/23] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 22/23] target/arm: Add isar_feature_{aa64,any}_ras, Peter Maydell, 2022/05/05
- [PULL 23/23] target/arm: read access to performance counters from EL0, Peter Maydell, 2022/05/05
- [PULL 21/23] target/arm: Add isar predicates for FEAT_Debugv8p2, Peter Maydell, 2022/05/05
- Re: [PULL 00/23] target-arm queue, Richard Henderson, 2022/05/05