[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 05/23] target/arm: Make some more cpreg data static const
From: |
Peter Maydell |
Subject: |
[PULL 05/23] target/arm: Make some more cpreg data static const |
Date: |
Thu, 5 May 2022 10:11:29 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
These particular data structures are not modified at runtime.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a68f14fe8e2..ca6ba9bd820 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7860,7 +7860,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.resetvalue = cpu->pmceid1 },
};
#ifdef CONFIG_USER_ONLY
- ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+ static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
{ .name = "ID_AA64PFR0_EL1",
.exported_bits = 0x000f000f00ff0000,
.fixed_bits = 0x0000000000000011 },
@@ -8000,7 +8000,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
*/
if (arm_feature(env, ARM_FEATURE_EL3)) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
- ARMCPRegInfo nsacr = {
+ static const ARMCPRegInfo nsacr = {
.name = "NSACR", .type = ARM_CP_CONST,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL1_RW, .accessfn = nsacr_access,
@@ -8008,7 +8008,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
};
define_one_arm_cp_reg(cpu, &nsacr);
} else {
- ARMCPRegInfo nsacr = {
+ static const ARMCPRegInfo nsacr = {
.name = "NSACR",
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL3_RW | PL1_R,
@@ -8019,7 +8019,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
} else {
if (arm_feature(env, ARM_FEATURE_V8)) {
- ARMCPRegInfo nsacr = {
+ static const ARMCPRegInfo nsacr = {
.name = "NSACR", .type = ARM_CP_CONST,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL1_R,
@@ -8172,13 +8172,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->pmsav7_dregion << 8
};
- ARMCPRegInfo crn0_wi_reginfo = {
+ static const ARMCPRegInfo crn0_wi_reginfo = {
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
.type = ARM_CP_NOP | ARM_CP_OVERRIDE
};
#ifdef CONFIG_USER_ONLY
- ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
+ static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
{ .name = "MIDR_EL1",
.exported_bits = 0x00000000ffffffff },
{ .name = "REVIDR_EL1" },
@@ -8223,7 +8223,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
};
#ifdef CONFIG_USER_ONLY
- ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
+ static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
{ .name = "MPIDR_EL1",
.fixed_bits = 0x0000000080000000 },
};
@@ -8302,7 +8302,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_VBAR)) {
- ARMCPRegInfo vbar_cp_reginfo[] = {
+ static const ARMCPRegInfo vbar_cp_reginfo[] = {
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
--
2.25.1
- [PULL 00/23] target-arm queue, Peter Maydell, 2022/05/05
- [PULL 01/23] target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user, Peter Maydell, 2022/05/05
- [PULL 03/23] target/arm: Reorg CPAccessResult and access_check_cp_reg, Peter Maydell, 2022/05/05
- [PULL 02/23] target/arm: Split out cpregs.h, Peter Maydell, 2022/05/05
- [PULL 05/23] target/arm: Make some more cpreg data static const,
Peter Maydell <=
- [PULL 06/23] target/arm: Reorg ARMCPRegInfo type field bits, Peter Maydell, 2022/05/05
- [PULL 08/23] target/arm: Change cpreg access permissions to enum, Peter Maydell, 2022/05/05
- [PULL 07/23] target/arm: Avoid bare abort() or assert(0), Peter Maydell, 2022/05/05
- [PULL 10/23] target/arm: Name CPSecureState type, Peter Maydell, 2022/05/05
- [PULL 09/23] target/arm: Name CPState type, Peter Maydell, 2022/05/05
- [PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h, Peter Maydell, 2022/05/05
- [PULL 13/23] target/arm: Merge allocation of the cpreg and its name, Peter Maydell, 2022/05/05
- [PULL 15/23] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases, Peter Maydell, 2022/05/05
- [PULL 17/23] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05