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[PATCH 6/7] target/mips: Add missing default cases for some nanoMips poo
From: |
Stefan Pejic |
Subject: |
[PATCH 6/7] target/mips: Add missing default cases for some nanoMips pools |
Date: |
Wed, 4 May 2022 13:04:02 +0200 |
Switch statements for the code segments that handle nanoMips
instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
do not have proper default case, resulting in not generating
reserved instruction exception for certain illegal opcodes.
Fix this by adding default cases for these switch statements that
trigger reserved instruction exception.
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
target/mips/tcg/nanomips_translate.c.inc | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/target/mips/tcg/nanomips_translate.c.inc
b/target/mips/tcg/nanomips_translate.c.inc
index 1ee5c8c8d4..c0ba2bf1b1 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2707,6 +2707,9 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs,
int rt)
case NM_SDC1XS:
tcg_gen_shli_tl(t0, t0, 3);
break;
+ default:
+ gen_reserved_instruction(ctx);
+ goto out;
}
}
gen_op_addr_add(ctx, t0, t0, t1);
@@ -2797,6 +2800,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs,
int rt)
break;
}
+out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@@ -3944,6 +3948,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_shift_imm(ctx, OPC_ROTR, rt, rs,
extract32(ctx->opcode, 0, 5));
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
}
break;
@@ -4245,6 +4252,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
check_xnp(ctx);
gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_P_SC:
@@ -4257,6 +4267,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
false);
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_CACHE:
@@ -4265,6 +4278,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_cache_operation(ctx, rt, rs, s);
}
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_P_LS_E0:
@@ -4371,6 +4387,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
}
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_P_LS_WM:
--
2.25.1
- [PATCH 0/7] Undeprecate nanoMIPS and fix multiple bugs, Stefan Pejic, 2022/05/04
- [PATCH 4/7] target/mips: Fix emulation of nanoMips BNEC[32] instruction, Stefan Pejic, 2022/05/04
- [PATCH 5/7] target/mips: Fix handling of unaligned memory access for nanoMips ISA, Stefan Pejic, 2022/05/04
- [PATCH 1/7] target/mips: Fix emulation of nanoMips MTHLIP instruction, Stefan Pejic, 2022/05/04
- [PATCH 3/7] target/mips: Fix emulation of nanoMips BPOSGE32C instruction, Stefan Pejic, 2022/05/04
- [PATCH 2/7] target/mips: Fix emulation of nanoMips EXTRV_S.H instruction, Stefan Pejic, 2022/05/04
- [PATCH 6/7] target/mips: Add missing default cases for some nanoMips pools,
Stefan Pejic <=
- [PATCH 7/7] target/mips: Undeprecate nanoMips ISA support in QEMU, Stefan Pejic, 2022/05/04