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[PATCH v4 40/45] target/arm: Enable FEAT_CSV2 for -cpu max
From: |
Richard Henderson |
Subject: |
[PATCH v4 40/45] target/arm: Enable FEAT_CSV2 for -cpu max |
Date: |
Sat, 30 Apr 2022 22:50:22 -0700 |
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index b200012d89..b2a3e2a437 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -12,6 +12,7 @@ the following architecture extensions:
- FEAT_BBM at level 2 (Translation table break-before-make levels)
- FEAT_BF16 (AArch64 BFloat16 instructions)
- FEAT_BTI (Branch Target Identification)
+- FEAT_CSV2 (Cache speculation variant 2)
- FEAT_DIT (Data Independent Timing instructions)
- FEAT_DPB (DC CVAP instruction)
- FEAT_Debugv8p2 (Debug changes for v8.2)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 10410619f9..25fe74f928 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -748,6 +748,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64pfr1;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index c5cf7efe95..762b961707 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -68,6 +68,7 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_mmfr4 = t;
t = cpu->isar.id_pfr0;
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
cpu->isar.id_pfr0 = t;
--
2.34.1
- [PATCH v4 07/45] target/arm: Change cpreg access permissions to enum, (continued)
- [PATCH v4 07/45] target/arm: Change cpreg access permissions to enum, Richard Henderson, 2022/05/01
- [PATCH v4 28/45] target/arm: Split out aa32_max_features, Richard Henderson, 2022/05/01
- [PATCH v4 33/45] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/05/01
- [PATCH v4 35/45] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/05/01
- [PATCH v4 37/45] target/arm: Implement ESB instruction, Richard Henderson, 2022/05/01
- [PATCH v4 19/45] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
- [PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2, Richard Henderson, 2022/05/01
- [PATCH v4 29/45] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/05/01
- [PATCH v4 36/45] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/05/01
- [PATCH v4 40/45] target/arm: Enable FEAT_CSV2 for -cpu max,
Richard Henderson <=
- [PATCH v4 41/45] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 44/45] target/arm: Define cortex-a76, Richard Henderson, 2022/05/01
- [PATCH v4 45/45] target/arm: Define neoverse-n1, Richard Henderson, 2022/05/01
- [PATCH v4 42/45] target/arm: Enable FEAT_CSV3 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 43/45] target/arm: Enable FEAT_DGH for -cpu max, Richard Henderson, 2022/05/01
- Re: [PATCH v4 00/45] target/arm: Cleanups, new features, new cpus, Peter Maydell, 2022/05/03