Implementing ATC[Address Translation Cache] within emulated pcie end-point

[Vishwanath MG]

  Looking for QEMU support in emulating ATC inside pcie EP (emulated). So
that ATC behaviour can be modelled, deriving right set of ATC parameters
and the right caching algorithm.

Looked at patches https://lists.nongnu.org/archive/html/qemu-devel/2016-11/msg00642.html
where ATS support has been added for  virtio kind of devices.

e.g, using virtio device
qemu-system-x86_64 \
    -machine q35,accel=kvm,kernel_irqchip=split \
    -enable-kvm \
    -vga none -nographic \
    -device intel-iommu,intremap=on,caching-mode=on,device-iotlb=on
    -device vfio-pci,host=03:00.0 \
    -device virtio-net-pci,netdev=mynet0,disable-legacy=on,disable-modern=off,iommu_platform=on,ats=on

In our use case, virtio-net-pci would be simple pcie EP, which implements ATC needs following infra
1. IOMMU invalidate request needs to be propagated to EP, so that ATC would be flushed
2. Ability to send ATS requests to the hypervisor layer to populate IOTLB entries
3. Ability to request for page to hypervisor, when page fault occurs at EP

exploring intel_iommu devices, to see if such a API;s are provided. Any help in this
would be highly appreciated.

thanks
Vishwa.mg ( @samsung)