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[PULL 31/32] hw/arm: ast2600: Fix address mapping of second SPI controll
From: |
Peter Maydell |
Subject: |
[PULL 31/32] hw/arm: ast2600: Fix address mapping of second SPI controller |
Date: |
Fri, 28 Jan 2022 15:30:08 +0000 |
From: Cédric Le Goater <clg@kaod.org>
Address should be 0x1E631000 and not 0x1E641000 as initially introduced.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/838
Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support")
Suggested-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220126083520.4135713-1-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/aspeed_ast2600.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 8f37bdb1d87..12f6edc081f 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -29,7 +29,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_PWM] = 0x1E610000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
- [ASPEED_DEV_SPI2] = 0x1E641000,
+ [ASPEED_DEV_SPI2] = 0x1E631000,
[ASPEED_DEV_EHCI1] = 0x1E6A1000,
[ASPEED_DEV_EHCI2] = 0x1E6A3000,
[ASPEED_DEV_MII1] = 0x1E650000,
--
2.25.1
- [PULL 06/32] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models, (continued)
- [PULL 06/32] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models, Peter Maydell, 2022/01/28
- [PULL 01/32] Update copyright dates to 2022, Peter Maydell, 2022/01/28
- [PULL 17/32] target/arm: Log CPU index in 'Taking exception' log, Peter Maydell, 2022/01/28
- [PULL 04/32] rtc: Move RTC function prototypes to their own header, Peter Maydell, 2022/01/28
- [PULL 07/32] hw/arm/xlnx-versal: Connect Versal's PMC SLCR, Peter Maydell, 2022/01/28
- [PULL 23/32] hw/intc/arm_gicv3_its: Sort ITS command list into numeric order, Peter Maydell, 2022/01/28
- [PULL 25/32] hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported, Peter Maydell, 2022/01/28
- [PULL 14/32] MAINTAINERS: Add an entry for Xilinx Versal OSPI, Peter Maydell, 2022/01/28
- [PULL 10/32] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller, Peter Maydell, 2022/01/28
- [PULL 13/32] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI, Peter Maydell, 2022/01/28
- [PULL 31/32] hw/arm: ast2600: Fix address mapping of second SPI controller,
Peter Maydell <=
- [PULL 15/32] MAINTAINERS: Remove myself (for raspi)., Peter Maydell, 2022/01/28
- [PULL 11/32] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model, Peter Maydell, 2022/01/28
- [PULL 20/32] hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set, Peter Maydell, 2022/01/28
- [PULL 26/32] hw/intc/arm_gicv3_its: Provide read accessor for translation_ops, Peter Maydell, 2022/01/28
- [PULL 03/32] hw/char/exynos4210_uart: Fix crash on trying to load VM state, Peter Maydell, 2022/01/28
- [PULL 21/32] hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER, Peter Maydell, 2022/01/28
- [PULL 08/32] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header, Peter Maydell, 2022/01/28
- [PULL 18/32] hw/intc/arm_gicv3_its: Add tracepoints, Peter Maydell, 2022/01/28
- [PULL 22/32] hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs, Peter Maydell, 2022/01/28
- [PULL 19/32] hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS, Peter Maydell, 2022/01/28